f87da95e57
jesd204: use jesd clock domain for sysref sampler
...
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
76fc63bbf7
jesd204: use separate controls for reset and input buffer disable
2018-06-22 11:38:18 +08:00
d9955fee76
jesd204: make sure IOB FF is used to sample SYSREF at FPGA
2018-06-22 11:00:56 +08:00
60b22217ce
sayma: set DRTIO master HMC830_REF to 100MHz
2018-06-22 10:10:09 +08:00
e6d1726754
sayma: add RTIO log to DRTIO master
2018-06-22 00:05:22 +08:00
83428961ad
sayma: add SAWG and JESD to DRTIO master
2018-06-22 00:04:22 +08:00
c1db02a351
drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
...
Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00
8b3c12e6eb
sayma: clock DRTIO master transceiver from HMC7043
2018-06-21 22:34:44 +08:00
de7d64d482
sayma: clock JESD204 from GTP CLK2
...
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
b28ff587c5
sayma: add sysref sampler to DRTIO master
2018-06-21 22:28:34 +08:00
e29536351d
drtio: resync SYSREF when TSC is loaded
2018-06-21 17:00:32 +08:00
45e8263208
hmc7043: do not configure phases during initial init
...
They are determined later on.
2018-06-21 15:54:42 +08:00
28fb0fd754
sayma: add SYSREF sampler gateware
2018-06-20 17:48:35 +08:00
9142a5ab8a
rtio: expose coarse timestamp in RTIO and DRTIO satellite cores
2018-06-20 17:39:54 +08:00
75b6cea52f
sayma: add SAWG to DRTIO satellite
2018-06-19 19:12:10 +08:00
433273dd95
sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite
2018-06-19 14:33:48 +08:00
6403a0d5d1
sayma_amc: update without-sawg description
2018-06-19 13:52:05 +08:00
d29b3dd588
hmc830: compile-time configurable reference frequency
2018-06-19 13:47:32 +08:00
6f3ed81626
targets/sayma_rtm: fix description
2018-06-18 17:46:53 +08:00
32484a62de
sayma_amc: remove unused imports
2018-06-17 13:09:44 +02:00
53ab255c00
sayma_amc: enable slave fpga loading ( #813 )
2018-06-16 12:47:26 +02:00
1029ac870b
sayma_rtm: don't drive txen pins
...
pins disabled by config
necessary for using that pin as DIN (#813 )
2018-06-13 16:11:30 +00:00
68d16fc292
serwb: support single-ended signals
...
Low-speed PHY only.
2018-06-13 21:28:21 +08:00
a9a25f2605
sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early
2018-06-12 20:00:12 +02:00
a143e238a8
savel_fpga: get rid of unneeded config
2018-06-12 10:24:04 +02:00
0b086225a9
sawg: don't use Cat() for signed signals
...
c.f. #1039 #1040 #1022 #1058 #1044
2018-06-09 07:33:47 +00:00
5b73dd8604
sawg: accurate unittest rtio freq
2018-06-08 17:22:13 +02:00
e5f6750171
sawg: cleanup double assign
2018-06-08 14:31:55 +00:00
Florent Kermarrec
53e9e475d0
serwb: transmit zeroes when nothing to transmit (for prbs), improve rx idle detection
2018-06-08 16:10:31 +02:00
Florent Kermarrec
7296a76f18
serwb: move common datapath code to datapath.py, simplify flow control
2018-06-08 12:37:08 +02:00
Florent Kermarrec
89797d08ed
serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds)
2018-06-07 15:13:56 +02:00
b4c2b148d1
sawg: don't use Mux for signed signals
...
migen#75
2018-06-06 15:51:14 +00:00
Florent Kermarrec
009db5eda9
serwb: revert 1gbps linerate
2018-06-06 16:20:20 +02:00
cae92f9b44
kasli: add Tsinghua variant
2018-06-06 19:03:45 +08:00
e21b7965b9
sayma_amc: change test patterns for 'without-sawg'
2018-06-06 08:02:52 +00:00
af88c4c93e
clean up hmc7043 reset
2018-06-05 20:41:48 +08:00
Thomas Harty
ac5c4913ec
Sayma RTM: hold hmc7043 in reset/mute state during init.
2018-06-05 19:22:04 +08:00
07d4145a35
correct documented siphaser VCO frequency [NFC]
2018-06-04 20:53:43 +08:00
bb87976d4f
suservo: docstring fixes, revert parametrization of r_rtt
2018-06-04 07:27:17 +00:00
07a1425e51
SUservo EEM docs
...
add documentation to eem.SUServo. Change parameterization of t_rtt to include delays on Sampler, as this seems simpler and more robust to changing RTIO frequencies in the future.
c.f. #1046
2018-06-04 08:51:28 +02:00
f50aef1a22
suservo: extract boilerplate
...
closes #1041
2018-06-01 15:37:07 +00:00
9b5a46dffd
suservo: fix restart counter assertion
...
c.f. #788
2018-05-31 15:56:11 +00:00
Paweł
44c7a028cb
Added second argument to DIO.add_STD in master and satellite variant of kasli (now builds properly)
2018-05-30 22:49:40 +08:00
ad099edf63
kasli: integrate grabber
2018-05-28 22:43:40 +08:00
563e434e15
eem: finalize grabber support
2018-05-28 22:43:06 +08:00
2612fd1e72
rtio: add grabber deserializer and WIP PHY encapsulation
2018-05-28 22:42:27 +08:00
Florent Kermarrec
e21f14c0b3
serwb/phy: typo (KUSSerdes --> KUSerdes)
2018-05-28 10:41:11 +02:00
b20a8c86b0
kasli: don't bother with grabber ttls for now
...
not used on target cameras
2018-05-28 07:31:00 +02:00
80c69da17e
eem: add Grabber IOs and CC
2018-05-28 11:16:23 +08:00
bb248970df
style
2018-05-28 10:40:05 +08:00
b09d07905c
kasli: add LUH/PTB/HUB variants
...
and refactor/simplify variant selection
2018-05-27 18:33:27 +00:00
Florent Kermarrec
bca2969957
sayma_rtm: add RTMScratch module to test remote Wishbone accesses
2018-05-24 16:53:10 +02:00
19efd8b13e
kasli: refactor EEM code
2018-05-24 18:41:54 +08:00
4e5fe672e7
kasli: add tester target
2018-05-21 17:43:39 +08:00
72aef5799e
kasli/ustc: use TTLOut
2018-05-18 22:55:28 +08:00
b10d3ee4b4
make RTIO clock switch optional and simplify
...
Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
2018-05-18 17:41:34 +08:00
8a988d0feb
kasli: remove leftover debug print
2018-05-18 17:25:23 +08:00
37bd0c2566
kasli: add USTC target
2018-05-18 16:15:07 +08:00
Florent Kermarrec
f77bcbebb5
serwb/test_serwb_core: fix
2018-05-16 08:34:53 +02:00
Florent Kermarrec
77fc5c599f
serwb/test: update
2018-05-15 23:52:58 +02:00
Florent Kermarrec
3873d09692
serwb: rewrite high-speed phys by splitting clocking/tx/rx, scrambling is now always enabled.
2018-05-15 23:52:41 +02:00
Florent Kermarrec
f8a9dd930b
serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled.
2018-05-15 23:51:14 +02:00
Florent Kermarrec
2c627cd061
serwb/scrambler: simplify and set scrambler input data to 0 when sink.stb == 0
2018-05-15 23:49:17 +02:00
Florent Kermarrec
c18a73d45f
sayma_amc/rtm: use new serwb low-speed phy
2018-05-15 16:40:50 +02:00
Florent Kermarrec
913d1e8e12
serwb: add generic low-speed phy (125Mhz linerate, same phy for ultrascale/7-series)
2018-05-15 16:39:39 +02:00
Florent Kermarrec
520aade8fe
serwb/scrambler: cleanup/fix potential bug
2018-05-15 16:30:52 +02:00
504d37b66b
suservo: add SI units functions and document
...
m-labs/artiq#788
2018-05-14 12:26:49 +00:00
d71e4e60a9
suservo: use addition for offset
2018-05-14 12:26:49 +00:00
27f975e7bb
kasli: eem DifferentialInputs need DIFF_TERM
...
cleanup some formatting on the way
2018-05-14 12:26:49 +00:00
2a47b934ea
suservo: remove adc return clock gating
2018-05-14 12:26:49 +00:00
74c0b4452b
suservo: clkout and sdo[b-d] are inverted
2018-05-14 12:26:49 +00:00
04240cdc08
suservo: sampler channels are reversed
2018-05-14 12:25:09 +00:00
3027951dd8
integrate new AD9914 driver
...
moninj, analyzer, docs, examples, tests.
2018-05-13 23:29:35 +08:00
whitequark
ee4c475cf3
gateware: fix Sayma satellite build.
...
RTIO clock multiplier was removed from Sayma in 32f22f4c
2018-05-13 13:10:39 +00:00
8c1390e557
kasli: use 62.5MHz clock for siphaser reference ( #999 )
2018-05-12 22:58:03 +08:00
2426fea3f2
siphaser: support external reference for the freerunning 150MHz
2018-05-12 22:57:11 +08:00
6796413a53
serwb: remove unnecessary shebang line
2018-05-12 22:49:44 +08:00
Florent Kermarrec
f5208ff2f3
serwb/core: reduce buffering, use buffered=True
2018-05-12 12:03:58 +02:00
Florent Kermarrec
fdc953e569
serwb/etherbone: recuce buffering
2018-05-12 12:03:11 +02:00
Florent Kermarrec
6e67e6d0b1
serwb: revert some changes (was breaking simulation)
2018-05-12 11:59:46 +02:00
Florent Kermarrec
0a6d4ccd85
serwb/phy: improve/cleanup init
2018-05-12 01:35:34 +02:00
Florent Kermarrec
b6ab59fb80
serwb/phy: increase timeout
2018-05-12 01:32:55 +02:00
Florent Kermarrec
e09dbc89bc
serwb: remove idelaye3 en_vtc (was not done correctly, we'll add direct software control)
2018-05-12 01:32:16 +02:00
Florent Kermarrec
cd4477864a
serwb: fix case when rtm fpga is not loaded, lvds input can be 0 or 1
2018-05-11 23:31:25 +02:00
2e3bf8602f
serwb: reduce buffering. Closes #997
2018-05-11 14:13:41 +08:00
6b811c1a8b
sayma: fix runtime/rtm gateware address conflict
2018-05-09 19:47:29 +08:00
f055bf88f6
suservo: add clip flags ( #992 )
2018-05-09 07:16:15 +00:00
Florent Kermarrec
60fd362d57
serwb: fix rx_comma detection
2018-05-07 23:54:35 +02:00
7d4a103a43
opticlock, suservo: set default kasli hw_rev
2018-05-07 09:07:18 +02:00
whitequark
b1d349cc1b
firmware: implement a sampling profiler.
...
Does not yet support constructing call graphs.
2018-05-05 00:44:40 +00:00
5f0cfadb30
rtio/sed: add unittest for sequence number rollover
2018-05-02 12:04:30 +08:00
4120105e3a
rtio/sed: fix output network cmp_wrap
2018-05-02 12:04:03 +08:00
bce8fa3ec5
rtio/sed: add replace unittest at the top level ( #978 )
2018-05-02 10:58:18 +08:00
83fb431cd0
rtio/sed: pass sequence numbers through the FIFOs. Closes #978
2018-05-02 10:57:57 +08:00
Florent Kermarrec
05955bfd79
sayma_rtm: use bufio for sys4x (needed since we are using a -1 speedgrade)
2018-05-01 22:16:35 +02:00
Florent Kermarrec
84e1f05559
sayma_rtm: make cd_sys4x clock domain reset_less
2018-05-01 16:11:26 +02:00
Florent Kermarrec
64c8eee28d
serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded)
2018-04-30 23:59:56 +02:00
5a683ddd1f
Revert "kasli: force hw_rev for the different targets"
...
This reverts commit 17d7d7856a
2018-04-28 23:24:41 +02:00
17d7d7856a
kasli: force hw_rev for the different targets
2018-04-28 21:30:29 +02:00
5d3c76fd50
sayma_rtm: use bitstream opts in migen
2018-04-27 15:43:32 +00:00
5f00326c65
suservo: coeff mem write port READ_FIRST
2018-04-27 15:43:32 +00:00
307cd07b9d
suservo: lots of gateware/ runtime changes
...
tested/validated:
* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback
individual changes below:
suservo: correct rtio readback
suservo: example, device_db [wip]
suservo: change rtio channel layout
suservo: mem ports in rio domain
suservo: sck clocked from rio_phy
suservo: cleanup, straighten out timing
suservo: dds cs polarity
suservo: simplify pipeline
suservo: drop unused eem names
suservo: decouple adc SR from IIR
suservo: expand coredevice layer
suservo: start the correct stage
suservo: actually load ctrl
suservo: refactor/tweak adc timing
suservo: implement cpld and dds init
2018-04-27 13:50:26 +02:00
Florent Kermarrec
8212e46f5e
sayma_amc: filter jesd refclk/sysref with jreset (hmc7043 can generate noise when unconfigured see sinara issue #541 )
2018-04-27 13:04:37 +02:00
f9b2c32739
suservo: add pgia spi channel
2018-04-25 17:14:25 +00:00
c83305065a
suservo: add servo/config/status register
2018-04-25 15:59:06 +00:00
105068ad90
suservo: fix restart timing
2018-04-25 15:19:49 +00:00
c304b6207a
suservo: drop adc idelays
2018-04-25 14:59:50 +00:00
b44d6517d1
suservo: use 125 MHz SDR ADC
...
* easier timing
* natural sampling on rising edge
* timing, signal robustness
* adjust the servo iteration timing
2018-04-25 14:32:23 +00:00
37c186a0fc
suservo: refactor, constrain
...
* remove DiffMixin, move pad layout handling to pads
* add input delay constraints, IDELAYs
2018-04-25 13:44:52 +00:00
d0258b9b2d
suservo: set input delays
2018-04-24 15:30:25 +00:00
fe75064c1e
suservo: cleanup rtio interface
2018-04-24 13:08:40 +00:00
3942c2d274
suservo: fix clkout cd drive
2018-04-24 10:18:32 +00:00
f74998a5e0
suservo: move arch logic to top, fix tests
2018-04-23 21:11:26 +00:00
4903eb074c
suservo: use BUFIO/BUFH for ADC
2018-04-23 18:30:19 +00:00
e36deab0a8
suservo/adc: try to help vivado extract srls
2018-04-23 18:30:19 +00:00
929ed4471b
kasli/SUServo: use suservo, implement urukul_qspi
...
m-labs/artiq#788
2018-04-23 18:30:18 +00:00
4c1e356f67
suservo: add pads rewiring layer for eems
2018-04-23 18:30:18 +00:00
99dd9c7a2a
suservo: fix rtio interface width
2018-04-23 18:30:18 +00:00
d5eea962ec
suservo: fix cnv_b diff
2018-04-23 18:30:12 +00:00
c8fd63754a
suservo: add unittests
...
m-labs/artiq#788
2018-04-23 18:25:59 +00:00
934c41b90a
gateware: add suservo
...
from
fe4b60b902m-labs/artiq#788
2018-04-23 18:24:59 +00:00
Florent Kermarrec
439d2bf2bc
sayma/serwb: adapt, full reset of rtm on link reset
2018-04-17 19:24:03 +02:00
Florent Kermarrec
8edf4541d6
serwb: adapt test
2018-04-17 19:21:53 +02:00
Florent Kermarrec
20ccc9d82f
serwb/core/phy: move scrambler in phy, add link test, revert delay min/max checks
2018-04-17 19:21:21 +02:00
Florent Kermarrec
ebfac36223
serwb/scrambler: dynamic enable/disable
2018-04-17 19:20:06 +02:00
Florent Kermarrec
816a6f2ec7
serwb/phys: remove phy_width (revert linerate to 1Gbps)
2018-04-17 19:19:18 +02:00
eac447278f
kasli: add MITLL variant
2018-04-17 19:00:11 +08:00
756e120c27
kasli/sysu: add comments
2018-04-17 18:46:55 +08:00
Florent Kermarrec
1acd7ea1db
sayma/serwb: re-enable scrambling
2018-04-17 00:49:36 +02:00
Florent Kermarrec
ca01c8f1cb
sayma: reduce serwb linerate to 500Mbps
2018-04-16 23:19:15 +02:00
Florent Kermarrec
825a2158ba
serwb: add phy_width parameter to allow reducing linerate to 500Mbps or 250Mbps
2018-04-16 23:19:14 +02:00
Florent Kermarrec
bb90fb7d59
sayma/serwb: remove scrambling (does not seems to work on sayma for now...)
2018-04-07 15:57:57 +02:00
Florent Kermarrec
6aa8e2c433
serwb/test: replace valid/ready with stb/ack
2018-04-07 15:55:57 +02:00
Florent Kermarrec
73dbc0b6b6
serwb/test: adapt to new version
2018-04-07 15:09:29 +02:00
Florent Kermarrec
e15f8aa903
sayma/serwb: enable scrambling
2018-04-07 14:52:37 +02:00
Florent Kermarrec
9d0e8c27ff
serwb/scrambler: add flow control
2018-04-07 14:51:17 +02:00
Florent Kermarrec
2f8bd022f7
sayma_rtm: remove sys0p2x clock
2018-04-07 03:10:34 +02:00
Florent Kermarrec
1fd96eb0fd
serwb: replace valid/ready with stb/ack
2018-04-07 03:06:19 +02:00
Florent Kermarrec
c8a08375f8
serwb: replace valid/ready with stb/ack
2018-04-07 03:03:44 +02:00
Florent Kermarrec
73b727cade
serwb: new version using only sys/sys4x clocks domains, scrambling deactivated.
2018-04-07 02:59:14 +02:00
Florent Kermarrec
dd21c07b85
targets/sayma_rtm: fix serwb 2 ...
2018-04-03 18:59:05 +02:00
Florent Kermarrec
7488703f23
targets/sayma_rtm: fix serwb
2018-04-03 18:57:00 +02:00
Florent Kermarrec
aef0153a8f
targets/sayma: adapt to new serwb clocking
2018-04-03 18:53:39 +02:00
Florent Kermarrec
3248caa184
gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks
2018-04-03 18:48:08 +02:00
f0771765c1
rtio: move CRI write comment to more appropriate location
2018-03-29 23:55:00 +08:00
493d2a653f
siphaser: add false path between sys_clk and mmcm_freerun_output
2018-03-29 10:55:41 +08:00
4229c045f4
kasli: fix DRTIO master clock constraint
2018-03-29 10:20:31 +08:00
3d89ba2e11
sayma: remove debug leftover
2018-03-29 10:20:17 +08:00
605292535c
kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well
2018-03-29 10:12:02 +08:00
whitequark
bab6723ff2
Revert "gateware: don't run tests if there is no migen."
...
This reverts commit 4804cfef9b
2018-03-26 03:33:52 +00:00
whitequark
4804cfef9b
gateware: don't run tests if there is no migen.
...
This allows us to skip testing gateware on Windows.
2018-03-26 03:26:34 +00:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
1553fc8c7d
sed: reset valid in output sorter
2018-03-23 11:11:11 +00:00
770b0a7b79
novogorny: conv -> cnv
...
* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
1afce8c613
kasli: simplify single eem pin formatting
2018-03-21 13:08:42 +01:00
d48b8f3086
kasli: fix sampler sdr/cnv pins
2018-03-21 09:28:00 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
...
Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
...
This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
c8020f6bbd
ttl_serdes_generic: fix/upgrade test
2018-03-20 16:46:57 +08:00
a5825184b7
add ttl_serdes_ultrascale (untested)
2018-03-20 16:07:23 +08:00
fad066f1aa
ttl_serdes_7series: cleanup indentation
...
Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
Thomas Harty
37d431039d
Fix typos.
...
Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
2fdc180601
dsp/fir: outputs reset_less (pipelined)
2018-03-13 17:11:50 +00:00
2edf65f57b
drtio: fix satellite minimum_coarse_timestamp clock domain ( #947 )
2018-03-13 00:20:57 +08:00
1d081ed6c2
drtio: print diagnostic info on satellite write underflow ( #947 )
2018-03-12 23:41:19 +08:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
...
They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
3fbcf5f303
drtio: remove TSC correction ( #40 )
2018-03-09 10:36:17 +08:00
e38187c760
drtio: increase default underflow margin. Closes #947
2018-03-09 00:49:24 +08:00
8bd15d36c4
drtio: fix error CSR edge detection ( #947 )
2018-03-08 16:28:25 +08:00
82831a85b6
kasli/opticlock: add eem6 phys
2018-03-07 21:32:59 +01:00
3a6566f949
rtio: judicious spray with reset_less=True
...
Hoping to reduce rst routing difficulty and easier RTIO timing closure.
2018-03-07 14:57:18 +00:00
b0282fa855
spi2: reset configuration in rio_phy
2018-03-07 14:42:11 +00:00
4af7600b2d
Revert "LaneDistributor: try equivalent spread logic"
...
This reverts commit 8b70db5f17
2018-03-07 11:34:51 +00:00
a6d1b030c1
RTIO: use TS counter in the correct CD
...
artiq/m-labs#938
2018-03-07 11:34:42 +00:00
8b70db5f17
LaneDistributor: try equivalent spread logic
2018-03-07 11:34:42 +00:00
2cbd597416
LaneDistributor: style and signal consolidation [NFC]
2018-03-07 11:34:42 +00:00
916197c4d7
siphaser: cleanup
2018-03-07 11:15:44 +08:00
f7aba6b570
siphaser: fix phase_shift_done CSR
2018-03-07 10:57:30 +08:00
acfd9db185
siphaser: minor cleanup
2018-03-07 10:57:30 +08:00
7d98864b31
sayma: enable siphaser
2018-03-07 10:57:30 +08:00
a6e29462a8
sayma: enable multilink DRTIO
2018-03-07 10:57:30 +08:00
c34d00cbc9
drtio: implement Si5324 phaser gateware and partial firmware support
2018-03-07 10:57:30 +08:00
994ceca9ff
sayma_amc: disable slave fpga gateware loading
2018-03-06 17:27:43 +01:00
62af7fe2ac
Revert "kasli/opticlock: use plain ttls for channels 8-23"
...
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.
No decrease in power consumption or improvement in timing.
2018-03-06 14:27:19 +01:00
fd3cdce59a
kasli/opticlock: use plain ttls for channels 8-23
2018-03-06 14:27:19 +01:00
50298a6104
ttl_serdes_7series: suppress diff_term in outputs
2018-03-06 14:27:19 +01:00
e356150ac4
ttl_simple: support differential io
2018-03-06 14:27:19 +01:00
956098c213
kasli: add second urukul, make clk_sel drive optional
2018-03-06 14:26:27 +01:00
07de7af86a
kasli: make second eem optional in urukul
2018-03-06 14:26:26 +01:00
c25560baec
sed: more LaneDistributor comments
2018-03-06 20:56:35 +08:00
f40255c968
sed: add comments about key points in LaneDistributor
2018-03-06 20:51:09 +08:00
Florent Kermarrec
5b3d6d57e2
drtio/gth: power down rx on restart (seems to make link initialization reliable)
2018-03-06 11:49:28 +01:00
Florent Kermarrec
64b05f07bb
drtio/gth: use parameters from Xilinx transceiver wizard
2018-03-06 11:02:15 +01:00
Florent Kermarrec
45f1e5a70e
drtio/gth: cleanup import
2018-03-06 10:56:07 +01:00
6aaa8bf9d9
drtio: fix link error generation
2018-03-04 23:20:13 +08:00
d747d74cb3
test: fix test_dma
2018-03-04 23:19:06 +08:00
928d5dc9b3
drtio: raise RTIOLinkError if operation fails due to link lost ( #942 )
2018-03-04 01:02:53 +08:00
ddcc68cff9
sayma_amc: move bitstream options to migen
...
close #930
2018-03-02 18:13:03 +08:00
a9daaad77b
kasli: add SYSU variant and device_db
2018-03-02 14:44:31 +08:00
cc70578f1f
remove old spi RTIO Phy
2018-03-01 11:19:18 +01:00
ec5b81da55
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
...
* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
54984f080b
artiq_flash: flash RTM firmware
...
based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:29:01 +01:00
1f999c7f5f
sayma_amc: expose RTM fpga load pins as GPIOs
2018-02-28 18:44:36 +01:00
Florent Kermarrec
2896dc619b
drtio/transceiver/gth: fix multilane
2018-02-28 14:15:40 +01:00
386aa75aaa
kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master
2018-02-27 23:18:18 +08:00
5d81877b34
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
2018-02-27 23:15:20 +08:00
Florent Kermarrec
1f0d955ce4
drtio/transceiver/gtp: implement tx multi lane phase alignment sequence
2018-02-27 12:32:25 +01:00
e565d3fa59
kasli: add analyzer and RTIO log to DRTIO master target
2018-02-27 18:09:07 +08:00
Florent Kermarrec
5b0f9cc6fd
drtio/transceiver/gth: fix single transceiver case
2018-02-23 12:15:47 +01:00
Florent Kermarrec
b4ba71c7a4
drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...)
2018-02-23 08:37:05 +01:00
Florent Kermarrec
820c834251
drtio/transceiver/gth: implement tx multi lane phase alignment sequence
2018-02-22 22:14:15 +01:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
...
m-labs/artiq#687
2018-02-22 17:19:51 +01:00
3b7971d15d
kasli: spelling
2018-02-22 17:19:51 +01:00
771bf87b56
kc705: port amc101_dac/spi0 and sma_spi to spi2
2018-02-22 17:19:51 +01:00
f8e6b4f4e3
ad5360: port to spi2
...
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
...
Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
a63fd306af
urukul: use spi2
...
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
37a0d6580b
spi2: add RTIO gateware and coredevice driver
...
1006218997
2018-02-21 13:37:36 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7a1d71502a
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
2018-02-21 13:37:29 +00:00
476e4fdd56
ttl_serdes_7series: disable IBUF and INTERM when output
2018-02-21 13:37:29 +00:00
f060d6e1b3
drtio: increase A7 clock aligner check period
2018-02-20 18:50:35 +08:00
f15b4bdde7
style
2018-02-20 18:47:59 +08:00
7d9c7ada71
drtio: fix test infinite loop
2018-02-20 17:42:00 +08:00
ad2c9590d0
drtio: rewrite/fix reset and link bringup/teardown
2018-02-20 17:26:43 +08:00
7e02d8245c
kasli: false paths
...
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
...
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
52049cf36a
drtio: add Xilinx RX synchronizer
2018-02-19 17:49:43 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
Florent Kermarrec
f5831af535
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
2018-02-19 10:03:19 +01:00
Florent Kermarrec
89a158c0c9
drtio/transceiver/gtp_7series_init: remove dead code
2018-02-19 10:02:23 +01:00
Florent Kermarrec
782051f474
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
2018-02-19 09:59:50 +01:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
94c20dfd4d
drtio: fix misleading GenericRXSynchronizer comment
2018-02-19 00:47:54 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
287d533437
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908 "
...
This reverts commit 2d4a1340ea
2018-02-17 17:38:48 +08:00
73985a9215
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
2018-02-17 17:38:17 +08:00
039dee4c8e
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
...
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
2018-02-17 13:54:50 +08:00
cfb21ca126
si5324: fix usage of external CLKIN2 reference
2018-02-17 13:52:01 +08:00
e41f49cc75
kasli: opticlock 125 MHz, mark external reference case broken
2018-02-16 17:23:15 +00:00
4d42df2a7c
kasli: set up Si5324 in standalone operation
2018-02-15 20:32:58 +08:00
d7387611c0
sayma: print RTM gateware version
2018-02-15 19:31:58 +08:00
be693bc8a9
opticlock: examples
2018-02-13 22:13:40 +01:00
a3d136d30d
opticlock: wire urukul and novogorny
2018-02-13 22:13:40 +01:00
ab5f397fea
sed/fifos: use AsyncFIFOBuffered
...
(D)RTIO now passes timing at 150MHz on Kasli.
2018-02-13 20:02:51 +08:00
00f42f912b
rename 'RTM identifier' to 'RTM magic number'
...
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
2018-02-13 20:02:51 +08:00
96b948f57f
remote_csr: add sanity check of CSR CSV type column
2018-02-13 20:02:51 +08:00
Florent Kermarrec
bfdda340fd
drtio/transceiver/gtp_7series: use parameters from xilinx wizard
2018-02-13 00:23:59 +01:00
Florent Kermarrec
180c28551d
drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
2018-02-09 20:17:02 +01:00
2d4a1340ea
sayma_amc: remove RTM bitstream upload core. Closes #908
2018-02-07 12:27:35 +08:00
whitequark
61c64a76be
gateware: use a per-variant subfolder in --output-dir. ( fixes #912 )
...
This commit also adds support for --variant and --args
to artiq-devtool.
2018-02-06 08:19:01 +00:00
whitequark
885ab40946
conda: split RTM and AMC packages back.
...
This avoids multiplying the RTM compilation time by the number
of AMC packages.
2018-01-28 14:27:55 +00:00
whitequark
11a8b84355
Merge the build trees of sayma_amc and sayma_rtm targets.
...
This also makes them a single artiq_flash target, and a single
conda package.
2018-01-27 19:54:31 +00:00
440e19b8f9
kasli: use SFP2 for DRTIO mastering
...
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
2018-01-26 19:02:54 +08:00
e0e795f11c
sayma_amc: constrain pin, remove keep
2018-01-23 15:42:47 +00:00
b5c035bb52
sayma_rtm: constrain serwb clock input
2018-01-23 13:54:53 +00:00
aada38f508
kasli, kc705: remove vivado "keep", cleanup a constraint
2018-01-23 13:15:26 +00:00
85102e191e
sayma_rtm: derive clocks automatically
...
* also don't add false paths unless necessary
2018-01-23 11:00:55 +00:00
7d1b3f37c9
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
2018-01-23 10:56:42 +00:00
649deccd9b
kasli: fix DRTIO satellite QPLL refclksel
2018-01-23 12:27:19 +08:00
4b4374f76a
sayma: register_jref for JESD204. Closes #904
2018-01-23 12:19:15 +08:00
763aefacff
kasli: fix typo
2018-01-23 12:10:54 +08:00
c7b148a704
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
2018-01-23 12:08:10 +08:00
d6157514c7
gtp_7series: flexible QPLL channel selection
2018-01-23 12:03:09 +08:00
9f87c34a94
kasli: fix QPLL instantiation
2018-01-23 10:39:31 +08:00
98a5607634
gtp_7series: set clock muxes correctly for second QPLL channel
2018-01-23 10:39:20 +08:00
25fee1a0bb
gtp_7series: use QPLL second channel
2018-01-23 10:15:49 +08:00
031d7ff020
kasli: keep using second QPLL channel for DRTIO satellite
2018-01-23 10:13:10 +08:00
626075cbc1
gtp_7series: simplify TX clocking
2018-01-23 09:49:23 +08:00
401e57d41c
gtp_7series: fix nchannels assert
2018-01-23 01:28:01 +08:00
aa62e91487
kasli: add DRTIO targets (no firmware)
2018-01-23 01:27:40 +08:00
296ac35f5d
sayma_amc: SFP TX disable is active-high
2018-01-23 00:32:09 +08:00
77192256ea
kc705: style
2018-01-23 00:02:35 +08:00
ab7c49d6d0
sayma_amc: raise error on invalid variant
2018-01-23 00:02:16 +08:00
c1ac3b66b1
sayma_rtm: fix 8fe463d4a
2018-01-23 00:01:45 +08:00
53facfef13
sayma: build fixes
2018-01-22 18:33:22 +08:00
25f3feeda8
refactor targets
2018-01-22 18:25:10 +08:00
5198c224a2
sayma,kasli: use new pin names
2018-01-22 11:51:07 +08:00
Florent Kermarrec
8fe463d4a0
sayma_rtm: add UART loopback to easily know if rtm fpga is alive
2018-01-20 06:04:34 +01:00
Florent Kermarrec
74ce7319d3
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
2018-01-20 06:04:18 +01:00
Florent Kermarrec
d27727968c
add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
2018-01-19 12:17:54 +01:00
cdbf95d46a
kasli: fix permissions
2018-01-19 18:31:20 +08:00
8ec33ae7bd
kasli: feed EEM clock fan-out from SI5324
2018-01-17 17:27:59 +01:00
ed3e3b2791
sayma_amc: clarify --with-sawg help
2018-01-17 12:10:30 +01:00
Florent Kermarrec
f54b27b79c
sayma_amc: prepare for jesd subclass 1
2018-01-17 11:49:36 +01:00
Florent Kermarrec
f73c3e5944
gateware/test/serwb: update and cleanup test (v2...)
2018-01-16 20:06:43 +01:00
7405006668
sayma: rtio clock is jesd fabric clock
2018-01-16 18:19:04 +01:00
whitequark
247167d34a
Revert "gateware/test/serwb: update and cleanup tests"
...
This reverts commit 5b03cc2fae
2018-01-16 08:21:26 +00:00
whitequark
444b901dbe
sayma: add RTM configuration port.
2018-01-16 07:28:00 +00:00
Florent Kermarrec
5b03cc2fae
gateware/test/serwb: update and cleanup tests
2018-01-15 21:53:40 +01:00
whitequark
6891141fa6
artiq_flash: add sayma support.
2018-01-15 11:43:29 +00:00
529033e016
kernel_cpu: disable PCU
...
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
2018-01-12 12:03:50 +00:00
ac3c3871d0
kasli: s/extensions/variant/g
2018-01-12 12:29:42 +01:00
7c82fcf41a
targets: avoid passing cpu_type around unnecessarily
2018-01-11 11:21:55 +08:00
6d58c4390b
Merge branch 'sed-merge'
2018-01-10 13:14:39 +08:00
04b2fd3e13
sayma: fix AD9154NoSAWG ramp clock domain
2018-01-10 12:11:33 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
Florent Kermarrec
2009734b3c
serwb/phy: get 625Mbps linerate working, increase timeout
2018-01-09 18:54:52 +01:00
Florent Kermarrec
9c6a7f7509
serwb/kusphy: use same serwb_serdes_5x reset than s7phy
2018-01-09 18:54:05 +01:00
8813aee6b1
targets: add kasli [wip, untested]
2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8
gateware/targets: enable serwb scrambling on sayma amc & rtm
2018-01-03 17:34:46 +01:00
Florent Kermarrec
907af25a69
gateware/serwb: add scrambling, reduce cdc fifo depth
2018-01-03 17:34:03 +01:00
Florent Kermarrec
7f4756a869
gateware/serwb: cleanup packet
2018-01-03 17:30:12 +01:00
c2be820e9a
kc705_dds: make ext_clkout 100 MHz
2018-01-02 19:58:47 +01:00
43686f324b
kc705_dds: fix HPC voltages
...
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V
* the direction control register on HPC (FMC-DIO to VHDCI)
was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
and hope for the best.
2018-01-02 13:41:07 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
53969d3686
kc705_dds: add urukul on vhdci extension definition
2018-01-02 13:20:47 +01:00
2f8e6c7462
spi: add diff_term, save power on outputs
2018-01-02 13:20:47 +01:00
6d20b71dde
ttl_serdes_7series: refactor IOSERDES
2018-01-02 13:20:47 +01:00
745e695b09
sayma: output a ramp in the absence of SAWG channels
2017-12-31 12:18:53 +01:00
whitequark
a371b25525
bootloader: allow using without Ethernet.
2017-12-31 09:21:28 +00:00
6e0288e568
drtio: fix GTH CPLL reset
2017-12-30 12:14:36 +08:00
379d29561b
sayma: plausibility assertion on sawg data stream
2017-12-29 19:15:40 +01:00
37f9c0b10c
spi: register clk
...
following m-labs/misoc#65
1dc68b0d0b
2017-12-28 16:50:22 +01:00
whitequark
acd13837ff
firmware: implement the new bootloader.
2017-12-28 13:18:51 +00:00
8153cfa88f
drtio/gth: add probes on {tx,rx}_init.done
2017-12-28 16:49:08 +08:00
c086149782
drtio/gth: use async microscope probes
2017-12-28 16:37:40 +08:00
whitequark
d94db1de5d
Revert accidentally committed parts of 1b9b5602.
2017-12-28 08:23:34 +00:00
whitequark
1b9b560242
firmware: use libbuild_misoc in libdrtioaux. NFC.
2017-12-28 08:20:23 +00:00
6801921fc0
drtio: instrument GTH transceiver
2017-12-28 15:03:14 +08:00
70b7f28ad3
drtio: drive SFP TX disable pins
2017-12-23 22:58:51 +08:00
f8c8f3fe26
drtio: fix GTH clock domains
2017-12-23 07:21:44 +08:00
1af21c0b29
drtio: integrate GTH transceiver for Sayma
2017-12-23 01:19:59 +08:00
c57b66497c
drtio: refactor/simplify GTH, use migen
2017-12-23 01:19:44 +08:00
77897228ca
drtio: add GTH transceiver code from Florent (197c79d47)
2017-12-22 18:01:28 +08:00
ebdbaaad32
drtio: remove KC705/GTX support
2017-12-22 17:51:42 +08:00
0681d472c7
conda: fix sayma_rtm_csr.csv location for Sayma AMC
2017-12-22 17:14:10 +08:00
44959144d8
conda: add Sayma AMC standalone board package
2017-12-22 16:44:04 +08:00
Florent Kermarrec
86825a852c
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
2017-12-21 23:52:44 +01:00
a6ffe9f38d
drtio: add Sayma top-level designs
2017-12-21 23:08:56 +08:00
4fbc8772a5
sayma: allocate all user LEDs to RTIO, make one TTL SMA input
2017-12-21 19:27:38 +08:00
a23251276d
Revert "sayma: set up Si5324 for RGMII clock rerouting"
...
This reverts commit 2b01aa22b6
2017-12-21 14:42:15 +08:00
2b01aa22b6
sayma: set up Si5324 for RGMII clock rerouting
2017-12-17 00:25:33 +08:00
b6199bb35b
sayma: style
2017-12-15 19:45:51 +08:00
649b60ea29
targets/kc705_drtio: remove DAC FMC card support
2017-12-15 17:32:25 +08:00
341e809859
targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator
2017-12-15 13:08:35 +08:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
5e251cd85c
sayma_amc: remove redundant bitstream options
...
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
2017-12-13 14:39:32 +01:00
a9d0f253a5
sayma_amc: set bitstream and config parameters
...
* slow down CCLK rate as there is additional loading
on the signals
* single bit SPI for now until we know that quad SPI
works
* set up
https://github.com/m-labs/artiq/issues/847
2017-12-13 21:21:52 +08:00
whitequark
1c25f7ef52
gateware: make software builds spew less junk on the console.
...
[ci skip]
2017-12-04 14:19:35 +00:00
bb3d6ef84a
sayma: remove ad9154 from mem_map
...
Address is autogenerated by CSR system.
2017-11-29 18:17:25 +08:00
ecfe2e40ee
sayma_amc_standalone: rtio channels for both sawg groups
2017-11-19 18:32:42 +01:00
d1a7c1c3a1
sayma_amc_standalone: connect sawg to jesd again
2017-11-19 14:36:20 +01:00
Florent Kermarrec
dfdd2dd9e6
gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb
2017-11-19 09:01:20 +01:00
Florent Kermarrec
cd83b71d92
gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping
2017-11-18 18:10:28 +01:00
Florent Kermarrec
f003566e52
serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...
...
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
2017-11-18 18:01:46 +01:00
Florent Kermarrec
1b976bfa4d
gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x
2017-11-18 17:57:11 +01:00
Florent Kermarrec
464b24a608
gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints.
2017-11-10 10:48:32 +01:00
Florent Kermarrec
278c739d30
gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints
2017-11-10 10:39:47 +01:00
Florent Kermarrec
48bfaec8d3
gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8
2017-11-10 10:37:08 +01:00
Florent Kermarrec
59be095512
gateware/serwb/kusphy: use locally inverted clk_b on iserdese3
2017-11-10 10:35:48 +01:00
Florent Kermarrec
db82b11f29
gateware/serwb/core: cleanup and increase fifo depth
2017-11-10 10:33:39 +01:00
Florent Kermarrec
76ddb063cf
gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation)
2017-11-06 12:08:28 +01:00
Florent Kermarrec
5bd1e43ced
gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender
2017-11-03 12:15:14 +01:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
d5b5076f67
gateware/ad5360_monitor: fix SPI data decoding
2017-10-26 11:58:59 +08:00
412548a86c
gateware: add AD5360 monitor (untested)
2017-10-23 20:09:28 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
4fa823b62a
gateware: add support for SPI-over-LVDS
2017-10-23 15:04:01 +08:00
893be82ad1
rtio/dma: raise underflow in test
2017-10-09 10:22:58 +08:00
a9c9d5779d
rtio/dma: add full-stack test with connection to RTIO core
2017-10-08 22:38:02 +08:00
5f083f21a4
rtio/dma: fix signal width
2017-10-08 22:37:46 +08:00
c7de233208
Merge Sayma SAWG changes (untested)
...
See #798
* sinara:
conda: bump migen
sayma_amc: SAWG (untested)
sayma_rtm: make build dir
conda: jesd204b 0.4
2017-09-29 21:01:02 +02:00
b4c52c34f7
Merge branch 'sinara'
2017-09-30 01:11:16 +08:00
6c049ad40c
rtio: report channel numbers in asynchronous errors
2017-09-29 16:32:57 +08:00
5437f0e3e3
rtio: make sequence errors consistently asychronous
2017-09-29 14:40:06 +08:00
5e3cc83842
sayma_amc: SAWG (untested)
2017-09-27 18:44:35 +02:00
2604806512
sayma_rtm: make build dir
2017-09-27 18:35:46 +02:00
73043c3464
drtio: disable SED lane spread
...
Doesn't improve things as the buffer space would still be determined
by the full FIFO, and adds unnecessary logic.
2017-09-26 16:46:09 +08:00
d7ef07a0c2
rtio/sed: document architecture
2017-09-26 16:44:23 +08:00
e6f0ce3aba
rtio/sed: test latency compensation
2017-09-26 16:11:21 +08:00
9905b8723b
rtio/sed: support negative latency compensation
2017-09-26 16:11:08 +08:00
f079ac6af6
rtio/sed: disable wait in TestLaneDistributor.test_regular
2017-09-26 16:10:52 +08:00
4112e403de
rtio/sed: latency compensation
2017-09-26 15:09:07 +08:00
e430d04d3f
drtio: remove obsolete import
2017-09-24 12:49:21 +08:00
20d79c930c
drtio: use SED and input collector
2017-09-24 12:23:47 +08:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
5cf0693758
rtio: use BlindTransfer to report collision and busy errors to sys domain
2017-09-21 22:31:56 +08:00
d74a7d272e
rtio: fix/cleanup parameters
2017-09-21 15:59:48 +08:00
07d3f87c51
rtio/sed: min_space → buffer_space
2017-09-21 14:36:13 +08:00
d8aa75b742
rtio/sed: add minimum buffer space reporting
2017-09-20 11:27:57 +08:00
63e39dec94
style
2017-09-20 11:26:12 +08:00
9ccd95e10d
drtio: remove spurious signals
2017-09-19 20:48:12 +08:00
7249f151a5
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:48:12 +08:00
171a2d19a0
drtio: remove spurious signals
2017-09-19 20:47:37 +08:00
1ff10785dc
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:46:16 +08:00
