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mirror of https://github.com/m-labs/artiq.git synced 2024-12-13 13:46:36 +08:00
artiq/artiq/gateware
2018-03-02 18:13:03 +08:00
..
amp refactor targets 2018-01-22 18:25:10 +08:00
drtio drtio/transceiver/gth: fix multilane 2018-02-28 14:15:40 +01:00
dsp Revert "sawg: advance dds 1/2 by one sample group" 2017-07-04 17:55:19 +02:00
rtio remove old spi RTIO Phy 2018-03-01 11:19:18 +01:00
serwb serwb/phy: get 625Mbps linerate working, increase timeout 2018-01-09 18:54:52 +01:00
targets sayma_amc: move bitstream options to migen 2018-03-02 18:13:03 +08:00
test drtio: fix test infinite loop 2018-02-20 17:42:00 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
remote_csr.py remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00