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suservo: remove adc return clock gating

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This commit is contained in:
Robert Jördens 2018-05-12 22:10:40 +00:00
parent 74c0b4452b
commit 2a47b934ea
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/suservo/adc_ser.py
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@ -107,7 +107,7 @@ class ADC(Module):
)
try:
sck_en_ret = pads.sck_en_ret
sck_en_ret = pads.sck_en_ret # simulation
except AttributeError:
sck_en_ret = 1
@ -119,7 +119,7 @@ class ADC(Module):
for i, sdo in enumerate(sdo):
sdo_sr = Signal(2*t_read)
self.sync.ret += [
If(self.reading & sck_en_ret,
If(sck_en_ret,
sdo_sr[1:].eq(sdo_sr),
sdo_sr[0].eq(sdo),
)