M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

dsp/fir: outputs reset_less (pipelined)

Browse Source
This commit is contained in:
Robert Jördens 2018-03-13 17:11:50 +00:00
parent 2edf65f57b
commit 2fdc180601
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/dsp/fir.py
View File

@ -69,7 +69,7 @@ class ParallelFIR(Module):
n = len(coefficients)
# input and output: old to new, decreasing delay
self.i = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True), reset_less=True) for i in range(p)]
self.latency = (n + 1)//2//p + 2
w = _widths[arch]