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drtio/transceiver/gth: implement tx multi lane phase alignment sequence
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@ -1,5 +1,5 @@
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from functools import reduce
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from operator import or_
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from operator import or_, and_
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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@ -16,7 +16,18 @@ from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
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class GTHSingle(Module):
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def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq, dw, mode):
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assert (dw == 20) or (dw == 40)
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assert mode in ["master", "slave"]
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assert mode in ["single", "master", "slave"]
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self.mode = mode
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# phase alignment
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self.txsyncallin = Signal()
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self.txphaligndone = Signal()
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self.txsyncallin = Signal()
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self.txsyncin = Signal()
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self.txsyncout = Signal()
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self.txdlysreset = Signal()
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# # #
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nwords = dw//10
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self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
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@ -96,11 +107,16 @@ class GTHSingle(Module):
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# TX Startup/Reset
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i_GTTXRESET=tx_init.gtXxreset,
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o_TXRESETDONE=tx_init.Xxresetdone,
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i_TXDLYSRESET=tx_init.Xxdlysreset,
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i_TXDLYSRESET=tx_init.Xxdlysreset if mode != "slave" else self.txdlysreset,
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o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
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o_TXPHALIGNDONE=tx_init.Xxphaligndone,
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i_TXUSERRDY=tx_init.Xxuserrdy,
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i_TXSYNCMODE=1,
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i_TXSYNCMODE=mode != "slave",
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p_TXSYNC_MULTILANE=0 if mode == "single" else 1,
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p_TXSYNC_OVRD=0,
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i_TXSYNCALLIN=self.txsyncallin,
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i_TXSYNCIN=self.txsyncin,
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o_TXSYNCOUT=self.txsyncout,
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# TX data
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p_TX_DATA_WIDTH=dw,
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@ -172,6 +188,7 @@ class GTHSingle(Module):
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o_GTHTXP=pads.txp,
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o_GTHTXN=pads.txn
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)
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self.comb += self.txphaligndone.eq(tx_init.Xxphaligndone)
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self.submodules += [
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add_probe_async("drtio_gth", "cpll_lock", cpll_lock),
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@ -221,6 +238,44 @@ class GTHSingle(Module):
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self.submodules += add_probe_async("drtio_gth", "clock_aligner_ready", clock_aligner.ready)
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class GTHTXPhaseAlignement(Module):
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# TX Buffer Bypass in Single-Lane/Multi-Lane Auto Mode (ug576)
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def __init__(self, gths):
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txsyncallin = Signal()
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txsync = Signal()
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txphaligndone = Signal(len(gths))
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txdlysreset = Signal()
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ready_for_align = Signal(len(gths))
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all_ready_for_align = Signal()
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for i, gth in enumerate(gths):
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# Common to all transceivers
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self.comb += [
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ready_for_align[i].eq(1),
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gth.txsyncin.eq(txsync),
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gth.txsyncallin.eq(txsyncallin),
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txphaligndone[i].eq(gth.txphaligndone)
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]
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# Specific to Master or Single transceivers
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if gth.mode == "master" or gth.mode == "single":
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self.comb += [
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gth.tx_init.all_ready_for_align.eq(all_ready_for_align),
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txsync.eq(gth.txsyncout),
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txdlysreset.eq(gth.tx_init.Xxdlysreset)
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]
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# Specific to Slave transceivers
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else:
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self.comb += [
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ready_for_align[i].eq(gth.tx_init.ready_for_align),
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gth.txdlysreset.eq(txdlysreset),
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]
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self.comb += [
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txsyncallin.eq(reduce(and_, [txphaligndone[i] for i in range(len(gths))])),
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all_ready_for_align.eq(reduce(and_, [ready_for_align[i] for i in range(len(gths))]))
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]
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class GTH(Module, TransceiverInterface):
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def __init__(self, clock_pads, data_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
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self.nchannels = nchannels = len(data_pads)
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@ -238,18 +293,23 @@ class GTH(Module, TransceiverInterface):
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rtio_tx_clk = Signal()
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channel_interfaces = []
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for i in range(nchannels):
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mode = "master" if i == master else "slave"
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gth = GTHSingle(refclk, data_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
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if mode == "master":
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self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
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if nchannels == 1:
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mode = "single"
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else:
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mode = "master" if i == master else "slave"
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gth = GTHSingle(plls[i], tx_pads[i], rx_pads[i], sys_clk_freq, dw, mode)
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if mode == "slave":
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self.comb += gth.cd_rtio_tx.clk.eq(rtio_tx_clk)
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else:
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self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
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self.gths.append(gth)
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setattr(self.submodules, "gth"+str(i), gth)
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channel_interface = ChannelInterface(gth.encoder, gth.decoders)
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self.comb += channel_interface.rx_ready.eq(gth.rx_ready)
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channel_interfaces.append(channel_interface)
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self.submodules.tx_phase_alignment = GTHTXPhaseAlignement(self.gths)
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TransceiverInterface.__init__(self, channel_interfaces)
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# GTH PLLs recover on their own from an interrupted clock input.
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# stable_clkin can be ignored.
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