drtio: disable SED lane spread

Doesn't improve things as the buffer space would still be determined by the full FIFO, and adds unnecessary logic.
2017-09-26 16:46:09 +08:00 · 2017-09-26 16:46:09 +08:00 · 73043c3464
parent d7ef07a0c2
commit 73043c3464
1 changed files with 2 additions and 1 deletions
--- a/artiq/gateware/drtio/core.py
+++ b/artiq/gateware/drtio/core.py
@ -91,7 +91,8 @@ class DRTIOSatellite(Module):
        self.submodules.outputs = ClockDomainsRenamer("rio")(
            SED(channels, fine_ts_width, "sync",
                lane_count=lane_count, fifo_depth=fifo_depth,
-                report_buffer_space=True, interface=self.rt_packet.cri))
+                enable_spread=False, report_buffer_space=True,
+                interface=self.rt_packet.cri))
        self.comb += self.outputs.coarse_timestamp.eq(coarse_ts)
        self.sync += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)