mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
ttl_serdes_generic: fix/upgrade test
This commit is contained in:
parent
a5825184b7
commit
c8020f6bbd
@ -115,166 +115,3 @@ class InOut(Module):
|
||||
self.submodules += pe
|
||||
self.comb += pe.i.eq(serdes.i ^ Replicate(i_d, serdes_width))
|
||||
self.sync.rio_phy += self.rtlink.i.fine_ts.eq(pe.o)
|
||||
|
||||
|
||||
class _FakeSerdes(Module):
|
||||
def __init__(self):
|
||||
self.o = Signal(8)
|
||||
self.i = Signal(8)
|
||||
self.oe = Signal()
|
||||
|
||||
|
||||
class _OutputTB(Module):
|
||||
def __init__(self):
|
||||
serdes = _FakeSerdes()
|
||||
self.submodules.dut = RenameClockDomains(Output(serdes),
|
||||
{"rio_phy": "sys"})
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
selfp.dut.rtlink.o.data = 1
|
||||
selfp.dut.rtlink.o.fine_ts = 1
|
||||
selfp.dut.rtlink.o.stb = 1
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
selfp.dut.rtlink.o.data = 0
|
||||
selfp.dut.rtlink.o.fine_ts = 2
|
||||
selfp.dut.rtlink.o.stb = 1
|
||||
yield
|
||||
yield
|
||||
selfp.dut.rtlink.o.data = 1
|
||||
selfp.dut.rtlink.o.fine_ts = 7
|
||||
selfp.dut.rtlink.o.stb = 1
|
||||
for _ in range(6):
|
||||
# note that stb stays active; output should not change
|
||||
yield
|
||||
|
||||
|
||||
class _InOutTB(Module):
|
||||
def __init__(self):
|
||||
self.serdes = _FakeSerdes()
|
||||
self.submodules.dut = RenameClockDomains(InOut(self.serdes),
|
||||
{"rio_phy": "sys",
|
||||
"rio": "sys"})
|
||||
|
||||
def check_input(self, selfp, stb, fine_ts=None):
|
||||
if stb != selfp.dut.rtlink.i.stb:
|
||||
print("KO rtlink.i.stb should be {} but is {}"
|
||||
.format(stb, selfp.dut.rtlink.i.stb))
|
||||
elif fine_ts is not None and fine_ts != selfp.dut.rtlink.i.fine_ts:
|
||||
print("KO rtlink.i.fine_ts should be {} but is {}"
|
||||
.format(fine_ts, selfp.dut.rtlink.i.fine_ts))
|
||||
else:
|
||||
print("OK")
|
||||
|
||||
def check_output(self, selfp, data):
|
||||
if selfp.serdes.o != data:
|
||||
print("KO io.o should be {} but is {}".format(data, selfp.serdes.o))
|
||||
else:
|
||||
print("OK")
|
||||
|
||||
def check_output_enable(self, selfp, oe):
|
||||
if selfp.serdes.oe != oe:
|
||||
print("KO io.oe should be {} but is {}".format(oe, selfp.serdes.oe))
|
||||
else:
|
||||
print("OK")
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
selfp.dut.rtlink.o.address = 2
|
||||
selfp.dut.rtlink.o.data = 0b11
|
||||
selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising + falling
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
|
||||
self.check_output_enable(selfp, 0)
|
||||
yield
|
||||
|
||||
selfp.serdes.i = 0b11111110 # rising edge at fine_ts = 1
|
||||
yield
|
||||
selfp.serdes.i = 0b11111111
|
||||
yield
|
||||
self.check_input(selfp, stb=1, fine_ts=1)
|
||||
|
||||
selfp.serdes.i = 0b01111111 # falling edge at fine_ts = 7
|
||||
yield
|
||||
selfp.serdes.i = 0b00000000
|
||||
yield
|
||||
self.check_input(selfp, stb=1, fine_ts=7)
|
||||
|
||||
selfp.serdes.i = 0b11000000 # rising edge at fine_ts = 6
|
||||
yield
|
||||
selfp.serdes.i = 0b11111111
|
||||
yield
|
||||
self.check_input(selfp, stb=1, fine_ts=6)
|
||||
|
||||
selfp.dut.rtlink.o.address = 2
|
||||
selfp.dut.rtlink.o.data = 0b11
|
||||
selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising only
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
|
||||
selfp.serdes.i = 0b00001111 # falling edge at fine_ts = 4
|
||||
yield
|
||||
self.check_input(selfp, stb=0) # no strobe, sensitivity is rising edge
|
||||
|
||||
selfp.serdes.i = 0b11110000 # rising edge at fine_ts = 4
|
||||
yield
|
||||
self.check_input(selfp, stb=1, fine_ts=4)
|
||||
|
||||
selfp.dut.rtlink.o.address = 1
|
||||
selfp.dut.rtlink.o.data = 1
|
||||
selfp.dut.rtlink.o.stb = 1 # set Output Enable to 1
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
yield
|
||||
self.check_output_enable(selfp, 1)
|
||||
|
||||
selfp.dut.rtlink.o.address = 0
|
||||
selfp.dut.rtlink.o.data = 1
|
||||
selfp.dut.rtlink.o.fine_ts = 3
|
||||
selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 3
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
self.check_output(selfp, data=0b11111000)
|
||||
|
||||
yield
|
||||
self.check_output(selfp, data=0xFF) # stays at 1
|
||||
|
||||
selfp.dut.rtlink.o.data = 0
|
||||
selfp.dut.rtlink.o.fine_ts = 0
|
||||
selfp.dut.rtlink.o.stb = 1 # falling edge at fine_ts = 0
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
self.check_output(selfp, data=0)
|
||||
|
||||
yield
|
||||
self.check_output(selfp, data=0)
|
||||
|
||||
selfp.dut.rtlink.o.data = 1
|
||||
selfp.dut.rtlink.o.fine_ts = 7
|
||||
selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 7
|
||||
yield
|
||||
selfp.dut.rtlink.o.stb = 0
|
||||
yield
|
||||
self.check_output(selfp, data=0b10000000)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
import sys
|
||||
from migen.sim.generic import Simulator, TopLevel
|
||||
|
||||
if len(sys.argv) != 2:
|
||||
print("Incorrect command line")
|
||||
sys.exit(1)
|
||||
|
||||
cls = {
|
||||
"output": _OutputTB,
|
||||
"inout": _InOutTB
|
||||
}[sys.argv[1]]
|
||||
|
||||
with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1/0.125))) as s:
|
||||
s.run()
|
||||
|
||||
125
artiq/gateware/test/rtio/test_ttl_serdes.py
Normal file
125
artiq/gateware/test/rtio/test_ttl_serdes.py
Normal file
@ -0,0 +1,125 @@
|
||||
import unittest
|
||||
|
||||
from migen import *
|
||||
|
||||
from artiq.gateware.rtio.phy.ttl_serdes_generic import *
|
||||
|
||||
|
||||
class _FakeSerdes:
|
||||
def __init__(self):
|
||||
self.o = Signal(8)
|
||||
self.i = Signal(8)
|
||||
self.oe = Signal()
|
||||
|
||||
|
||||
class _TB(Module):
|
||||
def __init__(self):
|
||||
self.serdes = _FakeSerdes()
|
||||
self.submodules.dut = ClockDomainsRenamer({"rio_phy": "sys", "rio": "sys"})(
|
||||
InOut(self.serdes))
|
||||
|
||||
|
||||
class TestTTLSerdes(unittest.TestCase):
|
||||
def test_input(self):
|
||||
tb = _TB()
|
||||
|
||||
def gen():
|
||||
yield tb.dut.rtlink.o.address.eq(2)
|
||||
yield tb.dut.rtlink.o.data.eq(0b11)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising + falling
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
|
||||
self.assertEqual((yield tb.serdes.oe), 0)
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
|
||||
|
||||
yield tb.serdes.i.eq(0b11111110) # rising edge at fine_ts = 1
|
||||
yield
|
||||
yield tb.serdes.i.eq(0b11111111)
|
||||
yield
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
|
||||
self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 1)
|
||||
|
||||
yield tb.serdes.i.eq(0b01111111) # falling edge at fine_ts = 7
|
||||
yield
|
||||
yield tb.serdes.i.eq(0b00000000)
|
||||
yield
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
|
||||
self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 7)
|
||||
|
||||
yield tb.serdes.i.eq(0b11000000) # rising edge at fine_ts = 6
|
||||
yield
|
||||
yield tb.serdes.i.eq(0b11111111)
|
||||
yield
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
|
||||
self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 6)
|
||||
|
||||
yield tb.dut.rtlink.o.address.eq(2)
|
||||
yield tb.dut.rtlink.o.data.eq(0b01)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising only
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
|
||||
yield tb.serdes.i.eq(0b00001111) # falling edge at fine_ts = 4
|
||||
yield
|
||||
yield tb.serdes.i.eq(0b00000000)
|
||||
yield
|
||||
# no strobe, sensitivity is rising edge
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
|
||||
|
||||
yield tb.serdes.i.eq(0b11110000) # rising edge at fine_ts = 4
|
||||
yield
|
||||
yield tb.serdes.i.eq(0b11111111)
|
||||
yield
|
||||
self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
|
||||
self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 4)
|
||||
|
||||
run_simulation(tb, gen())
|
||||
|
||||
def test_output(self):
|
||||
tb = _TB()
|
||||
|
||||
def gen():
|
||||
yield tb.dut.rtlink.o.address.eq(1)
|
||||
yield tb.dut.rtlink.o.data.eq(1)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # set Output Enable to 1
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.oe), 1)
|
||||
|
||||
yield tb.dut.rtlink.o.address.eq(0)
|
||||
yield tb.dut.rtlink.o.data.eq(1)
|
||||
yield tb.dut.rtlink.o.fine_ts.eq(3)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 3
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.o), 0b11111000)
|
||||
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.o), 0b11111111) # stays at 1
|
||||
|
||||
yield tb.dut.rtlink.o.data.eq(0)
|
||||
yield tb.dut.rtlink.o.fine_ts.eq(0)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # falling edge at fine_ts = 0
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.o), 0b00000000)
|
||||
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.o), 0b00000000)
|
||||
|
||||
yield tb.dut.rtlink.o.data.eq(1)
|
||||
yield tb.dut.rtlink.o.fine_ts.eq(7)
|
||||
yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 7
|
||||
yield
|
||||
yield tb.dut.rtlink.o.stb.eq(0)
|
||||
yield
|
||||
self.assertEqual((yield tb.serdes.o), 0b10000000)
|
||||
|
||||
run_simulation(tb, gen())
|
||||
Loading…
Reference in New Issue
Block a user