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kasli: add USTC target
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parent
73f8e61478
commit
37bd0c2566
189
artiq/examples/kasli_ustc/device_db.py
Normal file
189
artiq/examples/kasli_ustc/device_db.py
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@ -0,0 +1,189 @@
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core_addr = "kasli-2.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"i2c_switch0": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe0}
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},
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"i2c_switch1": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe2}
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},
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}
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for i in range(24):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut" if i < 4 else "TTLOut",
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"arguments": {"channel": i},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 24}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 25}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 26}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 27}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 125e6,
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"clk_sel": 0
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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}
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}
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device_db.update(
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spi_urukul1={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 30}
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},
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ttl_urukul1_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 31}
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},
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ttl_urukul1_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 32}
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},
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ttl_urukul1_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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},
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ttl_urukul1_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 34}
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},
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ttl_urukul1_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 35}
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},
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urukul1_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul1",
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"io_update_device": "ttl_urukul1_io_update",
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"refclk": 125e6,
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"clk_sel": 0
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}
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}
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)
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for i in range(4):
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device_db["urukul1_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"chip_select": 4 + i,
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"cpld_device": "urukul1_cpld",
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"sw_device": "ttl_urukul1_sw" + str(i)
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}
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}
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device_db.update(
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led0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 36}
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},
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led1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 37}
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}
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)
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82
artiq/examples/kasli_ustc/repository/demo.py
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82
artiq/examples/kasli_ustc/repository/demo.py
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@ -0,0 +1,82 @@
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from artiq.experiment import *
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class UrukulTest(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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self.setattr_device("urukul0_ch0")
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self.setattr_device("urukul0_ch1")
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self.setattr_device("urukul0_ch2")
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self.setattr_device("urukul0_ch3")
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self.setattr_device("urukul1_cpld")
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self.setattr_device("urukul1_ch0")
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self.setattr_device("urukul1_ch1")
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self.setattr_device("urukul1_ch2")
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self.setattr_device("urukul1_ch3")
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self.setattr_device("led0")
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self.ttl = self.get_device("ttl16")
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@kernel
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def run(self):
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self.core.reset()
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self.ttl.output()
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delay(1*us)
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self.urukul0_cpld.init()
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self.urukul0_ch0.init()
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self.urukul0_ch1.init()
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self.urukul0_ch2.init()
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self.urukul0_ch3.init()
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self.urukul1_cpld.init()
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self.urukul1_ch0.init()
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self.urukul1_ch1.init()
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self.urukul1_ch2.init()
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self.urukul1_ch3.init()
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delay(1000*us)
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self.urukul0_ch0.set(10*MHz)
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self.urukul0_ch0.sw.on()
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self.urukul0_ch0.set_att(10.)
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delay(1000*us)
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self.urukul0_ch1.set(20*MHz, 0.5)
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self.urukul0_ch1.sw.on()
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self.urukul0_ch1.set_att(8.)
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delay(1000*us)
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self.urukul0_ch2.set(30*MHz)
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self.urukul0_ch2.sw.on()
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self.urukul0_ch2.set_att(6.)
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delay(1000*us)
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self.urukul0_ch3.set(40*MHz)
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self.urukul0_ch3.sw.on()
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self.urukul0_ch3.set_att(4.)
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delay(1000*us)
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self.urukul1_ch0.set(15*MHz)
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self.urukul1_ch0.sw.on()
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self.urukul1_ch0.set_att(10.)
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delay(1000*us)
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self.urukul1_ch1.set(25*MHz, 0.5)
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self.urukul1_ch1.sw.on()
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self.urukul1_ch1.set_att(8.)
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delay(1000*us)
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self.urukul1_ch2.set(35*MHz)
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self.urukul1_ch2.sw.on()
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self.urukul1_ch2.set_att(6.)
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delay(1000*us)
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self.urukul1_ch3.set(45*MHz)
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self.urukul1_ch3.sw.on()
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self.urukul1_ch3.set_att(4.)
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while True:
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with parallel:
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self.ttl.pulse(100*ms)
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self.urukul0_ch0.sw.pulse(100*ms)
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delay(100*ms)
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self.led0.pulse(100*ms)
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@ -268,7 +268,8 @@ def main():
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},
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"kasli": {
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"programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"),
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"variants": ["opticlock", "suservo", "sysu", "mitll", "master", "satellite"],
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"variants": ["opticlock", "suservo", "sysu", "mitll", "ustc",
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"master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0x400000),
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"storage": ("spi0", 0x440000),
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@ -630,7 +630,11 @@ class SYSU(_StandaloneBase):
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for i in range(40):
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eem_offset, port = divmod(i, 8)
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pads = platform.request("eem{}".format(2 + eem_offset), port)
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phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
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if i < 4:
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cls = ttl_serdes_7series.InOut_8X
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else:
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cls = ttl_serdes_7series.Output_8X
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phy = cls(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -727,6 +731,63 @@ class MITLL(_StandaloneBase):
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self.add_rtio(rtio_channels)
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class USTC(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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platform = self.platform
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# TODO: grabber on eem0->eemA
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platform.add_extension(_urukul("eem2", "eem1"))
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platform.add_extension(_urukul("eem4", "eem3"))
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platform.add_extension(_dio("eem5"))
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platform.add_extension(_dio("eem6"))
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platform.add_extension(_dio("eem7"))
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# EEM5-7: TTL
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rtio_channels = []
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for i in range(24):
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eem_offset, port = divmod(i, 8)
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pads = platform.request("eem{}".format(5 + eem_offset), port)
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phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM2-4: Urukul
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for eem in (2, 4):
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phy = spi2.SPIMaster(self.platform.request("eem{}_spi_p".format(eem)),
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self.platform.request("eem{}_spi_n".format(eem)))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem{}_dds_reset".format(eem))
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem{}_{}".format(eem, signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp_ctl = platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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print(len(rtio_channels))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class _RTIOClockMultiplier(Module):
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def __init__(self, rtio_clk_freq):
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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@ -1037,7 +1098,8 @@ def main():
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock/suservo/sysu/mitll/master/satellite "
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help="variant: opticlock/suservo/sysu/mitll/ustc/"
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"master/satellite "
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"(default: %(default)s)")
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args = parser.parse_args()
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@ -1050,6 +1112,8 @@ def main():
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cls = SYSU
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elif variant == "mitll":
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cls = MITLL
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elif variant == "ustc":
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cls = USTC
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elif variant == "master":
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cls = Master
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elif variant == "satellite":
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