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kasli: eem DifferentialInputs need DIFF_TERM
cleanup some formatting on the way
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@ -6,21 +6,19 @@ from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from migen.genlib.io import DifferentialOutput, DifferentialInput
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from migen.genlib.io import DifferentialOutput
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores.a7_gtp import *
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from misoc.targets.kasli import (BaseSoC, MiniSoC,
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soc_kasli_args, soc_kasli_argdict)
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from misoc.targets.kasli import (
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BaseSoC, MiniSoC, soc_kasli_args, soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import (
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ttl_simple, ttl_serdes_7series, spi2, servo as rtservo)
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ttl_simple, ttl_serdes_7series, spi2, servo as rtservo)
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from artiq.gateware.suservo import servo, pads as servo_pads
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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@ -214,6 +212,7 @@ def _sampler(eem, eem_aux=None):
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Subsignal("sdob", Pins(_eem_pin(eem_aux, 2, "p"))),
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Subsignal("sdoc", Pins(_eem_pin(eem_aux, 3, "p"))),
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Subsignal("sdod", Pins(_eem_pin(eem_aux, 4, "p"))),
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Misc("DIFF_TERM=TRUE"),
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IOStandard("LVDS_25"),
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),
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("{}_adc_data_n".format(eem), 0,
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@ -222,6 +221,7 @@ def _sampler(eem, eem_aux=None):
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Subsignal("sdob", Pins(_eem_pin(eem_aux, 2, "n"))),
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Subsignal("sdoc", Pins(_eem_pin(eem_aux, 3, "n"))),
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Subsignal("sdod", Pins(_eem_pin(eem_aux, 4, "n"))),
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Misc("DIFF_TERM=TRUE"),
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IOStandard("LVDS_25"),
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),
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]
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