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serwb: revert 1gbps linerate
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cae92f9b44
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@ -200,7 +200,7 @@ class Standalone(MiniSoC, AMPSoC):
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master")
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serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master")
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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@ -42,8 +42,8 @@ class CRG(Module):
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
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p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1,
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 500MHz
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@ -181,8 +181,8 @@ class SaymaRTM(Module):
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 8.)
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serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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platform.add_period_constraint(serwb_pads.clk_p, 10.)
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serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += [
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self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
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