Sebastien Bourdeauducq 60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz		2018-06-22 10:10:09 +08:00
..
amp	refactor targets	2018-01-22 18:25:10 +08:00
drtio	drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin	2018-06-21 22:56:07 +08:00
dsp	sawg: don't use Cat() for signed signals	2018-06-09 07:33:47 +00:00
grabber	rtio: add grabber deserializer and WIP PHY encapsulation	2018-05-28 22:42:27 +08:00
rtio	rtio: expose coarse timestamp in RTIO and DRTIO satellite cores	2018-06-20 17:39:54 +08:00
serwb	serwb: support single-ended signals	2018-06-13 21:28:21 +08:00
suservo	suservo: fix restart counter assertion	2018-05-31 15:56:11 +00:00
targets	sayma: set DRTIO master HMC830_REF to 100MHz	2018-06-22 10:10:09 +08:00
test	sawg: accurate unittest rtio freq	2018-06-08 17:22:13 +02:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
eem.py	suservo: docstring fixes, revert parametrization of r_rtt	2018-06-04 07:27:17 +00:00
jesd204_tools.py	sayma: clock JESD204 from GTP CLK2	2018-06-21 22:33:53 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
remote_csr.py	remote_csr: add sanity check of CSR CSV type column	2018-02-13 20:02:51 +08:00