mirror of https://github.com/m-labs/artiq
drtio: refactor/simplify GTH, use migen
parent
77897228ca
commit
c57b66497c
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@ -1,113 +0,0 @@
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from math import ceil
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from functools import reduce
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from operator import add
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from litex.gen import *
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from litex.gen.genlib.cdc import MultiReg, PulseSynchronizer
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# Changes the phase of the transceiver RX clock to align the comma to
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# the LSBs of RXDATA, fixing the latency.
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#
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# This is implemented by repeatedly resetting the transceiver until it
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# gives out the correct phase. Each reset gives a random phase.
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#
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# If Xilinx had designed the GTX transceiver correctly, RXSLIDE_MODE=PMA
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# would achieve this faster and in a cleaner way. But:
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# * the phase jumps are of 2 UI at every second RXSLIDE pulse, instead
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# of 1 UI at every pulse. It is unclear what the latency becomes.
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# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# transceiver "feature".
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#
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class BruteforceClockAligner(Module):
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def __init__(self, comma, tx_clk_freq, check_period=6e-3):
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self.rxdata = Signal(20)
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self.restart = Signal()
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self.ready = Signal()
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check_max_val = ceil(check_period*tx_clk_freq)
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check_counter = Signal(max=check_max_val+1)
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check = Signal()
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reset_check_counter = Signal()
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self.sync.rtio_tx += [
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check.eq(0),
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If(reset_check_counter,
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check_counter.eq(check_max_val)
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).Else(
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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).Else(
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check_counter.eq(check_counter-1)
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)
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)
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]
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checks_reset = PulseSynchronizer("rtio_tx", "rtio_rx")
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self.submodules += checks_reset
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comma_n = ~comma & 0b1111111111
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
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comma_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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self.sync.rtio_rx += \
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If(checks_reset.o,
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comma_seen_rxclk.eq(0)
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).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
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comma_seen_rxclk.eq(1)
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)
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error_seen_rxclk = Signal()
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error_seen = Signal()
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error_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(error_seen_rxclk, error_seen)
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rx1cnt = Signal(max=11)
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self.sync.rtio_rx += [
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rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
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If(checks_reset.o,
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error_seen_rxclk.eq(0)
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).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
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error_seen_rxclk.eq(1)
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)
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]
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fsm = ClockDomainsRenamer("rtio_tx")(FSM(reset_state="WAIT_COMMA"))
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self.submodules += fsm
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fsm.act("WAIT_COMMA",
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If(check,
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# Errors are still OK at this stage, as the transceiver
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# has just been reset and may output garbage data.
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If(comma_seen,
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NextState("WAIT_NOERROR")
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).Else(
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self.restart.eq(1)
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("WAIT_NOERROR",
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If(check,
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If(comma_seen & ~error_seen,
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NextState("READY")
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).Else(
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("READY",
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reset_check_counter.eq(1),
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self.ready.eq(1),
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If(error_seen,
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checks_reset.i.eq(1),
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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)
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)
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@ -1,224 +1,26 @@
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from litex.gen import *
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from litex.gen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen.genlib.cdc import MultiReg
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import Encoder, Decoder
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from drtio.common import TransceiverInterface, ChannelInterface
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from drtio.gth_ultrascale_init import GTHInit
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from drtio.clock_aligner import BruteforceClockAligner
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class GTHChannelPLL(Module):
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def __init__(self, refclk, refclk_freq, linerate):
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self.refclk = refclk
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self.reset = Signal()
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self.lock = Signal()
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self.config = self.compute_config(refclk_freq, linerate)
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@staticmethod
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def compute_config(refclk_freq, linerate):
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for n1 in 4, 5:
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for n2 in 1, 2, 3, 4, 5:
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for m in 1, 2:
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vco_freq = refclk_freq*(n1*n2)/m
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if 2.0e9 <= vco_freq <= 6.25e9:
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for d in 1, 2, 4, 8, 16:
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current_linerate = vco_freq*2/d
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if current_linerate == linerate:
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return {"n1": n1, "n2": n2, "m": m, "d": d,
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"vco_freq": vco_freq,
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"clkin": refclk_freq,
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"linerate": linerate}
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msg = "No config found for {:3.2f} MHz refclk / {:3.2f} Gbps linerate."
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raise ValueError(msg.format(refclk_freq/1e6, linerate/1e9))
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def __repr__(self):
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r = """
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GTHChannelPLL
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==============
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overview:
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---------
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+--------------------------------------------------+
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| |
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| +-----+ +---------------------------+ +-----+ |
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| | | | Phase Frequency Detector | | | |
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CLKIN +----> /M +--> Charge Pump +-> VCO +---> CLKOUT
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| | | | Loop Filter | | | |
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| +-----+ +---------------------------+ +--+--+ |
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| ^ | |
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| | +-------+ +-------+ | |
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| +----+ /N2 <----+ /N1 <----+ |
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| +-------+ +-------+ |
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+--------------------------------------------------+
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+-------+
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CLKOUT +-> 2/D +-> LINERATE
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+-------+
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config:
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-------
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CLKIN = {clkin}MHz
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CLKOUT = CLKIN x (N1 x N2) / M = {clkin}MHz x ({n1} x {n2}) / {m}
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= {vco_freq}GHz
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LINERATE = CLKOUT x 2 / D = {vco_freq}GHz x 2 / {d}
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= {linerate}GHz
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""".format(clkin=self.config["clkin"]/1e6,
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n1=self.config["n1"],
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n2=self.config["n2"],
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m=self.config["m"],
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vco_freq=self.config["vco_freq"]/1e9,
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d=self.config["d"],
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linerate=self.config["linerate"]/1e9)
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return r
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class GTHQuadPLL(Module):
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def __init__(self, refclk, refclk_freq, linerate):
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self.clk = Signal()
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self.refclk = Signal()
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self.reset = Signal()
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self.lock = Signal()
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self.config = self.compute_config(refclk_freq, linerate)
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# # #
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self.specials += \
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Instance("GTHE3_COMMON",
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# common
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i_GTREFCLK00=refclk,
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i_GTREFCLK01=refclk,
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i_QPLLRSVD1=0,
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i_QPLLRSVD2=0,
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i_QPLLRSVD3=0,
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i_QPLLRSVD4=0,
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i_BGBYPASSB=1,
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i_BGMONITORENB=1,
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i_BGPDB=1,
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i_BGRCALOVRD=0b11111,
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i_BGRCALOVRDENB=0b1,
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i_RCALENB=1,
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# qpll0
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p_QPLL0_FBDIV=self.config["n"],
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p_QPLL0_REFCLK_DIV=self.config["m"],
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i_QPLL0CLKRSVD0=0,
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i_QPLL0CLKRSVD1=0,
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i_QPLL0LOCKDETCLK=ClockSignal(),
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i_QPLL0LOCKEN=1,
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o_QPLL0LOCK=self.lock if self.config["qpll"] == "qpll0" else
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Signal(),
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o_QPLL0OUTCLK=self.clk if self.config["qpll"] == "qpll0" else
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Signal(),
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o_QPLL0OUTREFCLK=self.refclk if self.config["qpll"] == "qpll0" else
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Signal(),
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i_QPLL0PD=0 if self.config["qpll"] == "qpll0" else 1,
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i_QPLL0REFCLKSEL=0b001,
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i_QPLL0RESET=self.reset,
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# qpll1
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p_QPLL1_FBDIV=self.config["n"],
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p_QPLL1_REFCLK_DIV=self.config["m"],
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i_QPLL1CLKRSVD0=0,
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i_QPLL1CLKRSVD1=0,
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i_QPLL1LOCKDETCLK=ClockSignal(),
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i_QPLL1LOCKEN=1,
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o_QPLL1LOCK=self.lock if self.config["qpll"] == "qpll1" else
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Signal(),
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o_QPLL1OUTCLK=self.clk if self.config["qpll"] == "qpll1" else
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Signal(),
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o_QPLL1OUTREFCLK=self.refclk if self.config["qpll"] == "qpll1" else
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Signal(),
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i_QPLL1PD=0 if self.config["qpll"] == "qpll1" else 1,
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i_QPLL1REFCLKSEL=0b001,
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i_QPLL1RESET=self.reset,
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)
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@staticmethod
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def compute_config(refclk_freq, linerate):
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for n in [16, 20, 32, 40, 60, 64, 66, 75, 80, 84,
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90, 96, 100, 112, 120, 125, 150, 160]:
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for m in 1, 2, 3, 4:
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vco_freq = refclk_freq*n/m
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if 8e9 <= vco_freq <= 13e9:
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qpll = "qpll1"
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elif 9.8e9 <= vco_freq <= 16.375e9:
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qpll = "qpll0"
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else:
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qpll = None
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if qpll is not None:
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for d in 1, 2, 4, 8, 16:
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current_linerate = (vco_freq/2)*2/d
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if current_linerate == linerate:
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return {"n": n, "m": m, "d": d,
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"vco_freq": vco_freq,
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"qpll": qpll,
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"clkin": refclk_freq,
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"clkout": vco_freq/2,
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"linerate": linerate}
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msg = "No config found for {:3.2f} MHz refclk / {:3.2f} Gbps linerate."
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raise ValueError(msg.format(refclk_freq/1e6, linerate/1e9))
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def __repr__(self):
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r = """
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GTXQuadPLL
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===========
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overview:
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---------
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+-------------------------------------------------------------++
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| +------------+ |
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| +-----+ +---------------------------+ | QPLL0 | +--+ |
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| | | | Phase Frequency Detector +-> VCO | | | |
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CLKIN +----> /M +--> Charge Pump | +------------+->/2+--> CLKOUT
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| | | | Loop Filter +-> QPLL1 | | | |
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| +-----+ +---------------------------+ | VCO | +--+ |
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| ^ +-----+------+ |
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| | +-------+ | |
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| +--------+ /N <----------------+ |
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| +-------+ |
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+--------------------------------------------------------------+
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+-------+
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CLKOUT +-> 2/D +-> LINERATE
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+-------+
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config:
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-------
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CLKIN = {clkin}MHz
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CLKOUT = CLKIN x N / (2 x M) = {clkin}MHz x {n} / (2 x {m})
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= {clkout}GHz
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VCO = {vco_freq}GHz ({qpll})
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LINERATE = CLKOUT x 2 / D = {clkout}GHz x 2 / {d}
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= {linerate}GHz
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""".format(clkin=self.config["clkin"]/1e6,
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n=self.config["n"],
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m=self.config["m"],
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clkout=self.config["clkout"]/1e9,
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vco_freq=self.config["vco_freq"]/1e9,
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qpll=self.config["qpll"].upper(),
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d=self.config["d"],
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linerate=self.config["linerate"]/1e9)
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return r
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
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class GTHSingle(Module):
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def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, dw=20, mode="master"):
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def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw, mode):
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assert (dw == 20) or (dw == 40)
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assert mode in ["master", "slave"]
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# # #
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nwords = dw//10
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use_cpll = isinstance(pll, GTHChannelPLL)
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use_qpll0 = isinstance(pll, GTHQuadPLL) and pll.config["qpll"] == "qpll0"
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use_qpll1 = isinstance(pll, GTHQuadPLL) and pll.config["qpll"] == "qpll1"
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self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
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Encoder(nwords, True))
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self.submodules.decoders = decoders = [ClockDomainsRenamer("rtio_rx")(
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(Decoder(True))) for _ in range(nwords)]
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self.rx_ready = Signal()
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self.rtio_clk_freq = pll.config["linerate"]/dw
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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@ -230,11 +32,13 @@ class GTHSingle(Module):
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tx_init = GTHInit(sys_clk_freq, False)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio_tx")(
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GTHInit(self.rtio_clk_freq, True))
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GTHInit(rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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pll_lock = Signal()
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self.comb += [
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tx_init.plllock.eq(pll.lock),
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rx_init.plllock.eq(pll.lock)
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tx_init.plllock.eq(pll_lock),
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rx_init.plllock.eq(pll_lock)
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]
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txdata = Signal(dw)
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@ -263,31 +67,25 @@ class GTHSingle(Module):
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p_CPLL_CFG1=0xa4ac,
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p_CPLL_CFG2=0xf007,
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p_CPLL_CFG3=0x0000,
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p_CPLL_FBDIV=1 if use_qpll0 or use_qpll1 else pll.config["n2"],
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p_CPLL_FBDIV_45=4 if use_qpll0 or use_qpll1 else pll.config["n1"],
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p_CPLL_REFCLK_DIV=1 if use_qpll0 or use_qpll1 else pll.config["m"],
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p_RXOUT_DIV=pll.config["d"],
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p_TXOUT_DIV=pll.config["d"],
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p_CPLL_FBDIV=5,
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p_CPLL_FBDIV_45=4,
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p_CPLL_REFCLK_DIV=1,
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p_RXOUT_DIV=2,
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p_TXOUT_DIV=2,
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i_CPLLRESET=0,
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i_CPLLPD=0 if use_qpll0 or use_qpll1 else pll.reset,
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o_CPLLLOCK=Signal() if use_qpll0 or use_qpll1 else pll.lock,
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i_CPLLPD=0,
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o_CPLLLOCK=pll_lock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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i_TSTIN=2**20-1,
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i_GTREFCLK0=0 if use_qpll0 or use_qpll1 else pll.refclk,
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# QPLL
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i_QPLL0CLK=0 if use_cpll or use_qpll1 else pll.clk,
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i_QPLL0REFCLK=0 if use_cpll or use_qpll1 else pll.refclk,
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i_QPLL1CLK=0 if use_cpll or use_qpll0 else pll.clk,
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i_QPLL1REFCLK=0 if use_cpll or use_qpll0 else pll.refclk,
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i_GTREFCLK0=refclk,
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00 if use_cpll else 0b10 if use_qpll0 else 0b11,
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i_TXPLLCLKSEL=0b00 if use_cpll else 0b11 if use_qpll0 else 0b10,
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i_TXSYSCLKSEL=0b00,
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i_TXPLLCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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@ -376,11 +174,9 @@ class GTHSingle(Module):
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio_tx = ClockDomain()
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if mode == "master":
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tx_bufg_div = pll.config["clkin"]/self.rtio_clk_freq
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assert tx_bufg_div == int(tx_bufg_div)
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self.specials += \
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Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk,
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i_DIV=int(tx_bufg_div)-1)
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i_DIV=0)
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self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
|
||||
|
||||
# rx clocking
|
||||
|
|
@ -401,7 +197,7 @@ class GTHSingle(Module):
|
|||
self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)])
|
||||
|
||||
# clock alignment
|
||||
clock_aligner = BruteforceClockAligner(0b0101111100, self.rtio_clk_freq)
|
||||
clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq)
|
||||
self.submodules += clock_aligner
|
||||
self.comb += [
|
||||
clock_aligner.rxdata.eq(rxdata),
|
||||
|
|
@ -411,19 +207,24 @@ class GTHSingle(Module):
|
|||
|
||||
|
||||
class GTH(Module, TransceiverInterface):
|
||||
def __init__(self, plls, tx_pads, rx_pads, sys_clk_freq, dw, master=0):
|
||||
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
|
||||
self.nchannels = nchannels = len(tx_pads)
|
||||
self.gths = []
|
||||
|
||||
# # #
|
||||
|
||||
nwords = dw//10
|
||||
refclk = Signal()
|
||||
self.specials += Instance("IBUFDS_GTE3",
|
||||
i_CEB=0,
|
||||
i_I=clock_pads.p,
|
||||
i_IB=clock_pads.n,
|
||||
o_O=refclk)
|
||||
|
||||
rtio_tx_clk = Signal()
|
||||
channel_interfaces = []
|
||||
for i in range(nchannels):
|
||||
mode = "master" if i == master else "slave"
|
||||
gth = GTHSingle(plls[i], tx_pads[i], rx_pads[i], sys_clk_freq, dw, mode)
|
||||
gth = GTHSingle(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
|
||||
if mode == "master":
|
||||
self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
|
||||
else:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,13 @@
|
|||
from math import ceil
|
||||
from functools import reduce
|
||||
from operator import add
|
||||
|
||||
from litex.gen import *
|
||||
from litex.gen.genlib.cdc import MultiReg
|
||||
from litex.gen.genlib.misc import WaitTimer
|
||||
from migen import *
|
||||
from migen.genlib.cdc import MultiReg, PulseSynchronizer
|
||||
from migen.genlib.misc import WaitTimer
|
||||
|
||||
|
||||
__all__ = ["BruteforceClockAligner", "GTHInit"]
|
||||
|
||||
|
||||
class GTHInit(Module):
|
||||
|
|
@ -135,3 +140,111 @@ class GTHInit(Module):
|
|||
self.done.eq(1),
|
||||
If(self.restart, NextState("RESET_ALL"))
|
||||
)
|
||||
|
||||
|
||||
# Changes the phase of the transceiver RX clock to align the comma to
|
||||
# the LSBs of RXDATA, fixing the latency.
|
||||
#
|
||||
# This is implemented by repeatedly resetting the transceiver until it
|
||||
# gives out the correct phase. Each reset gives a random phase.
|
||||
#
|
||||
# If Xilinx had designed the GTX transceiver correctly, RXSLIDE_MODE=PMA
|
||||
# would achieve this faster and in a cleaner way. But:
|
||||
# * the phase jumps are of 2 UI at every second RXSLIDE pulse, instead
|
||||
# of 1 UI at every pulse. It is unclear what the latency becomes.
|
||||
# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
|
||||
# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
|
||||
# transceiver "feature".
|
||||
#
|
||||
# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
|
||||
# compared to the usual 8b10b binary representation.
|
||||
class BruteforceClockAligner(Module):
|
||||
def __init__(self, comma, tx_clk_freq, check_period=6e-3):
|
||||
self.rxdata = Signal(20)
|
||||
self.restart = Signal()
|
||||
|
||||
self.ready = Signal()
|
||||
|
||||
check_max_val = ceil(check_period*tx_clk_freq)
|
||||
check_counter = Signal(max=check_max_val+1)
|
||||
check = Signal()
|
||||
reset_check_counter = Signal()
|
||||
self.sync.rtio_tx += [
|
||||
check.eq(0),
|
||||
If(reset_check_counter,
|
||||
check_counter.eq(check_max_val)
|
||||
).Else(
|
||||
If(check_counter == 0,
|
||||
check.eq(1),
|
||||
check_counter.eq(check_max_val)
|
||||
).Else(
|
||||
check_counter.eq(check_counter-1)
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
checks_reset = PulseSynchronizer("rtio_tx", "rtio_rx")
|
||||
self.submodules += checks_reset
|
||||
|
||||
comma_n = ~comma & 0b1111111111
|
||||
comma_seen_rxclk = Signal()
|
||||
comma_seen = Signal()
|
||||
comma_seen_rxclk.attr.add("no_retiming")
|
||||
self.specials += MultiReg(comma_seen_rxclk, comma_seen)
|
||||
self.sync.rtio_rx += \
|
||||
If(checks_reset.o,
|
||||
comma_seen_rxclk.eq(0)
|
||||
).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
|
||||
comma_seen_rxclk.eq(1)
|
||||
)
|
||||
|
||||
error_seen_rxclk = Signal()
|
||||
error_seen = Signal()
|
||||
error_seen_rxclk.attr.add("no_retiming")
|
||||
self.specials += MultiReg(error_seen_rxclk, error_seen)
|
||||
rx1cnt = Signal(max=11)
|
||||
self.sync.rtio_rx += [
|
||||
rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
|
||||
If(checks_reset.o,
|
||||
error_seen_rxclk.eq(0)
|
||||
).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
|
||||
error_seen_rxclk.eq(1)
|
||||
)
|
||||
]
|
||||
|
||||
fsm = ClockDomainsRenamer("rtio_tx")(FSM(reset_state="WAIT_COMMA"))
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("WAIT_COMMA",
|
||||
If(check,
|
||||
# Errors are still OK at this stage, as the transceiver
|
||||
# has just been reset and may output garbage data.
|
||||
If(comma_seen,
|
||||
NextState("WAIT_NOERROR")
|
||||
).Else(
|
||||
self.restart.eq(1)
|
||||
),
|
||||
checks_reset.i.eq(1)
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_NOERROR",
|
||||
If(check,
|
||||
If(comma_seen & ~error_seen,
|
||||
NextState("READY")
|
||||
).Else(
|
||||
self.restart.eq(1),
|
||||
NextState("WAIT_COMMA")
|
||||
),
|
||||
checks_reset.i.eq(1)
|
||||
)
|
||||
)
|
||||
fsm.act("READY",
|
||||
reset_check_counter.eq(1),
|
||||
self.ready.eq(1),
|
||||
If(error_seen,
|
||||
checks_reset.i.eq(1),
|
||||
self.restart.eq(1),
|
||||
NextState("WAIT_COMMA")
|
||||
)
|
||||
)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue