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mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 21:26:37 +08:00
artiq/artiq/gateware
2018-06-04 07:27:17 +00:00
..
amp refactor targets 2018-01-22 18:25:10 +08:00
drtio siphaser: support external reference for the freerunning 150MHz 2018-05-12 22:57:11 +08:00
dsp dsp/fir: outputs reset_less (pipelined) 2018-03-13 17:11:50 +00:00
grabber rtio: add grabber deserializer and WIP PHY encapsulation 2018-05-28 22:42:27 +08:00
rtio rtio: add grabber deserializer and WIP PHY encapsulation 2018-05-28 22:42:27 +08:00
serwb serwb/phy: typo (KUSSerdes --> KUSerdes) 2018-05-28 10:41:11 +02:00
suservo suservo: fix restart counter assertion 2018-05-31 15:56:11 +00:00
targets suservo: extract boilerplate 2018-06-01 15:37:07 +00:00
test serwb/test_serwb_core: fix 2018-05-16 08:34:53 +02:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
eem.py suservo: docstring fixes, revert parametrization of r_rtt 2018-06-04 07:27:17 +00:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
remote_csr.py remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00