jesd204: use jesd clock domain for sysref sampler

RTIO domain is still in reset during calibration.
2018-06-22 17:12:59 +08:00 · 2018-06-22 17:12:59 +08:00 · f87da95e57
parent 76fc63bbf7
commit f87da95e57
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/jesd204_tools.py
+++ b/artiq/gateware/jesd204_tools.py
@ -108,5 +108,5 @@ class SysrefSampler(Module, AutoCSR):
        self.sample_result = CSRStatus()

        sample = Signal()
-        self.sync.rtio += If(coarse_ts[:4] == 0, sample.eq(jref))
+        self.sync.jesd += If(coarse_ts[:4] == 0, sample.eq(jref))
        self.specials += MultiReg(sample, self.sample_result.status)