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serwb/core/phy: move scrambler in phy, add link test, revert delay min/max checks
This commit is contained in:
Florent Kermarrec
parent
ebfac36223
commit
20ccc9d82f
@ -2,13 +2,12 @@ from migen import *
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from misoc.interconnect import stream
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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from artiq.gateware.serwb.packet import Packetizer, Depacketizer
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from artiq.gateware.serwb.etherbone import Etherbone
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class SERWBCore(Module):
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def __init__(self, phy, clk_freq, mode, with_scrambling=False):
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def __init__(self, phy, clk_freq, mode):
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# etherbone
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self.submodules.etherbone = etherbone = Etherbone(mode)
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@ -22,31 +21,14 @@ class SERWBCore(Module):
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rx_fifo = stream.SyncFIFO([("data", 32)], 16)
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self.submodules += tx_fifo, rx_fifo
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# scrambling
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scrambler = Scrambler(enable=with_scrambling)
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descrambler = Descrambler(enable=with_scrambling)
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self.submodules += scrambler, descrambler
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# modules connection
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self.comb += [
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# core --> phy
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packetizer.source.connect(tx_fifo.sink),
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tx_fifo.source.connect(scrambler.sink),
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If(phy.init.ready,
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If(scrambler.source.stb,
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phy.serdes.tx_k.eq(scrambler.source.k),
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phy.serdes.tx_d.eq(scrambler.source.d)
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),
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scrambler.source.ack.eq(phy.serdes.tx_ce)
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),
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tx_fifo.source.connect(phy.sink),
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# phy --> core
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If(phy.init.ready,
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descrambler.sink.stb.eq(phy.serdes.rx_ce),
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descrambler.sink.k.eq(phy.serdes.rx_k),
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descrambler.sink.d.eq(phy.serdes.rx_d)
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),
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descrambler.source.connect(rx_fifo.sink),
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phy.source.connect(rx_fifo.sink),
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rx_fifo.source.connect(depacketizer.sink),
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# etherbone <--> core
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@ -2,8 +2,10 @@ from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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from artiq.gateware.serwb.kusphy import KUSSerdes
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from artiq.gateware.serwb.s7phy import S7Serdes
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@ -110,7 +112,9 @@ class _SerdesMasterInit(Module):
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_max - delay_min) < taps//16,
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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NextValue(delay_min_found, 0),
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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@ -231,7 +235,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_max - delay_min) < taps//16,
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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NextValue(delay_min_found, 0),
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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@ -289,18 +295,25 @@ class _SerdesControl(Module, AutoCSR):
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self.delay_max = CSRStatus(9)
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self.bitslip = CSRStatus(6)
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self.scrambling_enable = CSRStorage()
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self.prbs_error = Signal()
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self.prbs_start = CSR()
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self.prbs_cycles = CSRStorage(32)
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self.prbs_errors = CSRStatus(32)
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# # #
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if mode == "master":
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# In Master mode, reset is coming from CSR,
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# it resets the Master that will also reset
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# the Slave by putting the link in idle.
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self.comb += init.reset.eq(self.reset.re)
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self.sync += init.reset.eq(self.reset.re)
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else:
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# In Slave mode, reset is coming from link,
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# Master reset the Slave by putting the link
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# in idle.
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self.comb += [
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self.sync += [
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init.reset.eq(serdes.rx_idle),
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serdes.reset.eq(serdes.rx_idle)
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]
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@ -315,20 +328,81 @@ class _SerdesControl(Module, AutoCSR):
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self.bitslip.status.eq(init.bitslip)
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]
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# prbs
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prbs_cycles = Signal(32)
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prbs_errors = self.prbs_errors.status
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prbs_fsm = FSM(reset_state="IDLE")
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self.submodules += prbs_fsm
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prbs_fsm.act("IDLE",
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NextValue(prbs_cycles, 0),
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If(self.prbs_start.re,
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NextValue(prbs_errors, 0),
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NextState("CHECK")
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)
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)
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prbs_fsm.act("CHECK",
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NextValue(prbs_cycles, prbs_cycles + 1),
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If(self.prbs_error,
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NextValue(prbs_errors, prbs_errors + 1),
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),
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If(prbs_cycles == self.prbs_cycles.storage,
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NextState("IDLE")
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)
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)
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class SERWBPHY(Module, AutoCSR):
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def __init__(self, device, pads, mode="master", phy_width=8):
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def __init__(self, device, pads, mode="master", init_timeout=2**14):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("data", 32)])
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assert mode in ["master", "slave"]
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if device[:4] == "xcku":
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taps = 512
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self.submodules.serdes = KUSSerdes(pads, mode, phy_width)
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self.submodules.serdes = KUSSerdes(pads, mode)
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elif device[:4] == "xc7a":
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taps = 32
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self.submodules.serdes = S7Serdes(pads, mode, phy_width)
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self.submodules.serdes = S7Serdes(pads, mode)
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else:
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raise NotImplementedError
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if mode == "master":
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self.submodules.init = _SerdesMasterInit(self.serdes, taps)
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self.submodules.init = _SerdesMasterInit(self.serdes, taps, init_timeout)
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else:
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self.submodules.init = _SerdesSlaveInit(self.serdes, taps)
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self.submodules.init = _SerdesSlaveInit(self.serdes, taps, init_timeout)
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self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
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# scrambling
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scrambler = Scrambler()
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descrambler = Descrambler()
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self.submodules += scrambler, descrambler
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self.comb += [
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scrambler.enable.eq(self.control.scrambling_enable.storage),
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descrambler.enable.eq(self.control.scrambling_enable.storage)
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]
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# tx dataflow
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self.comb += \
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If(self.init.ready,
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sink.connect(scrambler.sink),
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scrambler.source.ack.eq(self.serdes.tx_ce),
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If(scrambler.source.stb,
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self.serdes.tx_d.eq(scrambler.source.d),
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self.serdes.tx_k.eq(scrambler.source.k)
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)
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)
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# rx dataflow
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self.comb += [
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If(self.init.ready,
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descrambler.sink.stb.eq(self.serdes.rx_ce),
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descrambler.sink.d.eq(self.serdes.rx_d),
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descrambler.sink.k.eq(self.serdes.rx_k),
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descrambler.source.connect(source)
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),
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# For PRBS test we are using the scrambler/descrambler as PRBS,
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# sending 0 to the scrambler and checking that descrambler
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# output is always 0.
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self.control.prbs_error.eq(
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descrambler.source.stb &
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descrambler.source.ack &
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(descrambler.source.data != 0))
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]
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