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sayma: add RTIO log to DRTIO master

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This commit is contained in:
Sebastien Bourdeauducq 2018-06-22 00:05:22 +08:00
parent 83428961ad
commit e6d1726754
1 changed files with 4 additions and 0 deletions
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4
artiq/gateware/targets/sayma_amc.py
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@ -313,6 +313,10 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")