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kasli: use 62.5MHz clock for siphaser reference (#999)

pull/1017/head
Sebastien Bourdeauducq 2018-05-12 22:57:34 +08:00
parent 2426fea3f2
commit 8c1390e557
1 changed files with 2 additions and 1 deletions
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3
artiq/gateware/targets/kasli.py
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@ -934,7 +934,8 @@ class _SatelliteBase(BaseSoC):
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"),
ref_clk=self.crg.clk125_div2, ref_div2=True)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")