rtio/dma: fix signal width

2017-10-08 22:37:46 +08:00 · 2017-10-08 22:37:46 +08:00 · 5f083f21a4
parent 6c049ad40c
commit 5f083f21a4
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@ -254,7 +254,7 @@ class CRIMaster(Module, AutoCSR):

        # # #

-        underflow_trigger = Signal(2)
+        underflow_trigger = Signal()
        self.sync += [
            If(underflow_trigger,
                self.underflow.w.eq(1),