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rtio/dma: fix signal width

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This commit is contained in:
Sebastien Bourdeauducq 2017-10-08 22:37:46 +08:00
parent 6c049ad40c
commit 5f083f21a4
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/dma.py
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@ -254,7 +254,7 @@ class CRIMaster(Module, AutoCSR):
# # #
underflow_trigger = Signal(2)
underflow_trigger = Signal()
self.sync += [
If(underflow_trigger,
self.underflow.w.eq(1),