M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

serwb: revert some changes (was breaking simulation)

This commit is contained in:
Florent Kermarrec 2018-05-12 11:59:46 +02:00
parent 0a6d4ccd85
commit 6e67e6d0b1
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
artiq/gateware/serwb/phy.py
View File

@ -121,9 +121,9 @@ class _SerdesMasterInit(Module):
If((delay_min == 0) |
(delay_max == (taps - 1)) |
((delay_max - delay_min) < taps//16),
# switch to next bitslip
NextValue(delay, taps - 1),
NextState("INC_DELAY_BITSLIP")
NextValue(delay_min_found, 0),
NextValue(delay_max_found, 0),
NextState("WAIT_STABLE")
).Else(
NextValue(delay, 0),
serdes.rx_delay_rst.eq(1),
@ -238,9 +238,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
If((delay_min == 0) |
(delay_max == (taps - 1)) |
((delay_max - delay_min) < taps//16),
# switch to next bitslip
NextValue(delay, taps - 1),
NextState("INC_DELAY_BITSLIP")
NextValue(delay_min_found, 0),
NextValue(delay_max_found, 0),
NextState("WAIT_STABLE")
).Else(
NextValue(delay, 0),
serdes.rx_delay_rst.eq(1),
@ -258,9 +258,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
serdes.tx_idle.eq(1)
)
fsm.act("SEND_PATTERN",
If(~serdes.rx_comma,
timer.wait.eq(1),
If(timer.done,
timer.wait.eq(1),
If(timer.done,
If(~serdes.rx_comma,
NextState("READY")
)
),