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drtio: fix satellite minimum_coarse_timestamp clock domain (#947)

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This commit is contained in:
Sebastien Bourdeauducq 2018-03-13 00:20:57 +08:00
parent 999ec40e79
commit 2edf65f57b
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/core.py
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@ -97,7 +97,7 @@ class DRTIOSatellite(Module):
enable_spread=False, report_buffer_space=True,
interface=self.rt_packet.cri))
self.comb += self.outputs.coarse_timestamp.eq(coarse_ts)
self.sync += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)
self.sync.rtio += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)
self.submodules.inputs = ClockDomainsRenamer("rio")(
InputCollector(channels, fine_ts_width, "sync",