mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
sayma_rtm: remove sys0p2x clock
This commit is contained in:
parent
1fd96eb0fd
commit
2f8bd022f7
@ -21,7 +21,6 @@ from artiq import __version__ as artiq_version
|
||||
|
||||
class CRG(Module):
|
||||
def __init__(self, platform):
|
||||
self.clock_domains.cd_sys0p2x = ClockDomain()
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_sys4x = ClockDomain()
|
||||
self.clock_domains.cd_clk200 = ClockDomain()
|
||||
@ -30,7 +29,6 @@ class CRG(Module):
|
||||
|
||||
pll_locked = Signal()
|
||||
pll_fb = Signal()
|
||||
pll_sys0p2x = Signal()
|
||||
pll_sys = Signal()
|
||||
pll_sys4x = Signal()
|
||||
pll_clk200 = Signal()
|
||||
@ -43,23 +41,18 @@ class CRG(Module):
|
||||
p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKIN1=self.serwb_refclk, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
|
||||
|
||||
# 25MHz
|
||||
p_CLKOUT0_DIVIDE=40, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys0p2x,
|
||||
|
||||
# 125MHz
|
||||
p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys,
|
||||
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
|
||||
|
||||
# 500MHz
|
||||
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_sys4x,
|
||||
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
|
||||
|
||||
# 200MHz
|
||||
p_CLKOUT3_DIVIDE=5, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200
|
||||
p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200
|
||||
),
|
||||
Instance("BUFG", i_I=pll_sys0p2x, o_O=self.cd_sys0p2x.clk),
|
||||
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
|
||||
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
|
||||
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
|
||||
AsyncResetSynchronizer(self.cd_sys0p2x, ~pll_locked),
|
||||
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
|
||||
AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked),
|
||||
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked)
|
||||
|
Loading…
Reference in New Issue
Block a user