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gtp_7series: set clock muxes correctly for second QPLL channel
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@ -86,7 +86,7 @@ class GTPSingle(Module):
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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p_TXOUT_DIV=2,
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i_TXSYSCLKSEL=0b00,
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i_TXSYSCLKSEL=0b11,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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@ -136,7 +136,7 @@ class GTPSingle(Module):
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p_TX_CLK25_DIV=5,
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p_RX_XCLK_SEL="RXUSR",
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p_RXOUT_DIV=2,
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i_RXSYSCLKSEL=0b00,
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i_RXSYSCLKSEL=0b11,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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