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drtio: fix link error generation

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This commit is contained in:
Sebastien Bourdeauducq 2018-03-04 23:20:13 +08:00
parent d747d74cb3
commit 6aaa8bf9d9
1 changed files with 3 additions and 7 deletions
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10
artiq/gateware/drtio/rt_controller_master.py
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@ -63,11 +63,6 @@ class RTController(Module):
self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio"))
self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset)
self.comb += [
self.cri.o_status[2].eq(~self.csrs.link_up.storage),
self.cri.i_status[3].eq(~self.csrs.link_up.storage)
]
# protocol errors
err_unknown_packet_type = Signal()
err_packet_truncated = Signal()
@ -126,7 +121,7 @@ class RTController(Module):
o_status_underflow = Signal()
self.comb += [
self.cri.o_status.eq(Cat(
o_status_wait, o_status_underflow)),
o_status_wait, o_status_underflow, ~self.csrs.link_up.storage)),
self.csrs.o_wait.status.eq(o_status_wait)
]
o_underflow_set = Signal()
@ -151,7 +146,8 @@ class RTController(Module):
i_status_overflow = Signal()
i_status_wait_status = Signal()
self.comb += self.cri.i_status.eq(Cat(
i_status_wait_event, i_status_overflow, i_status_wait_status))
i_status_wait_event, i_status_overflow, i_status_wait_status,
~self.csrs.link_up.storage))
load_read_reply = Signal()
self.sync.sys_with_rst += [