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gateware/serwb: add scrambling, reduce cdc fifo depth
This commit is contained in:
Florent Kermarrec
parent
7f4756a869
commit
907af25a69
@ -2,38 +2,54 @@ from migen import *
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from misoc.interconnect import stream
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from artiq.gateware.serwb.packet import Depacketizer, Packetizer
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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from artiq.gateware.serwb.packet import Packetizer, Depacketizer
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from artiq.gateware.serwb.etherbone import Etherbone
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class SERWBCore(Module):
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def __init__(self, phy, clk_freq, mode):
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def __init__(self, phy, clk_freq, mode, with_scrambling=False):
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# etherbone
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self.submodules.etherbone = etherbone = Etherbone(mode)
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# packetizer / depacketizer
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depacketizer = Depacketizer(clk_freq)
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packetizer = Packetizer()
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self.submodules += depacketizer, packetizer
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tx_cdc = stream.AsyncFIFO([("data", 32)], 32)
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tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serwb_serdes"})(tx_cdc)
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self.submodules += tx_cdc
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rx_cdc = stream.AsyncFIFO([("data", 32)], 32)
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rx_cdc = ClockDomainsRenamer({"write": "serwb_serdes", "read": "sys"})(rx_cdc)
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self.submodules += rx_cdc
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self.comb += [
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# core <--> etherbone
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depacketizer.source.connect(etherbone.sink),
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etherbone.source.connect(packetizer.sink),
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# core --> serdes
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# clock domain crossing
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tx_cdc = stream.AsyncFIFO([("data", 32)], 16)
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tx_cdc = ClockDomainsRenamer({"write": "sys", "read": phy.cd})(tx_cdc)
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rx_cdc = stream.AsyncFIFO([("data", 32)], 16)
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rx_cdc = ClockDomainsRenamer({"write": phy.cd, "read": "sys"})(rx_cdc)
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self.submodules += tx_cdc, rx_cdc
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# scrambling
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scrambler = ClockDomainsRenamer(phy.cd)(Scrambler(enable=with_scrambling))
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descrambler = ClockDomainsRenamer(phy.cd)(Descrambler(enable=with_scrambling))
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self.submodules += scrambler, descrambler
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# modules connection
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self.comb += [
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# core --> phy
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packetizer.source.connect(tx_cdc.sink),
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tx_cdc.source.connect(scrambler.sink),
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If(phy.init.ready,
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If(tx_cdc.source.stb,
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phy.serdes.tx_data.eq(tx_cdc.source.data)
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If(scrambler.source.stb,
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phy.serdes.tx_k.eq(scrambler.source.k),
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phy.serdes.tx_d.eq(scrambler.source.d)
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),
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tx_cdc.source.ack.eq(1)
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scrambler.source.ack.eq(1)
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),
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# serdes --> core
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rx_cdc.sink.stb.eq(phy.init.ready),
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rx_cdc.sink.data.eq(phy.serdes.rx_data),
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# phy --> core
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descrambler.sink.stb.eq(phy.init.ready),
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descrambler.sink.k.eq(phy.serdes.rx_k),
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descrambler.sink.d.eq(phy.serdes.rx_d),
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descrambler.source.connect(rx_cdc.sink),
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rx_cdc.source.connect(depacketizer.sink),
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# etherbone <--> core
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depacketizer.source.connect(etherbone.sink),
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etherbone.source.connect(packetizer.sink)
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]
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@ -8,8 +8,10 @@ from misoc.cores.code_8b10b import Encoder, Decoder
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class KUSSerdes(Module):
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def __init__(self, pll, pads, mode="master"):
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self.tx_data = Signal(32)
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self.rx_data = Signal(32)
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self.tx_k = Signal(4)
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self.tx_d = Signal(32)
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self.rx_k = Signal(4)
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self.rx_d = Signal(32)
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self.tx_idle = Signal()
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self.tx_comma = Signal()
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@ -111,10 +113,14 @@ class KUSSerdes(Module):
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(0xbc)
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).Else(
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self.encoder.d[0].eq(self.tx_data[0:8]),
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self.encoder.d[1].eq(self.tx_data[8:16]),
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self.encoder.d[2].eq(self.tx_data[16:24]),
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self.encoder.d[3].eq(self.tx_data[24:32])
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self.encoder.k[0].eq(self.tx_k[0]),
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self.encoder.k[1].eq(self.tx_k[1]),
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self.encoder.k[2].eq(self.tx_k[2]),
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self.encoder.k[3].eq(self.tx_k[3]),
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self.encoder.d[0].eq(self.tx_d[0:8]),
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self.encoder.d[1].eq(self.tx_d[8:16]),
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self.encoder.d[2].eq(self.tx_d[16:24]),
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self.encoder.d[3].eq(self.tx_d[24:32])
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)
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]
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self.sync.serwb_serdes += \
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@ -217,7 +223,8 @@ class KUSSerdes(Module):
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self.decoders[1].input.eq(self.rx_bitslip.o[10:20]),
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self.decoders[2].input.eq(self.rx_bitslip.o[20:30]),
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self.decoders[3].input.eq(self.rx_bitslip.o[30:40]),
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self.rx_data.eq(Cat(*[self.decoders[i].d for i in range(4)])),
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self.rx_k.eq(Cat(*[self.decoders[i].k for i in range(4)])),
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self.rx_d.eq(Cat(*[self.decoders[i].d for i in range(4)])),
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rx_idle.eq(self.rx_bitslip.o == 0),
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rx_comma.eq(((self.decoders[0].d == 0xbc) & (self.decoders[0].k == 1)) &
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((self.decoders[1].d == 0x00) & (self.decoders[1].k == 0)) &
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@ -376,6 +376,7 @@ class SERWBPLL(Module):
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class SERWBPHY(Module, AutoCSR):
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cd = "serwb_serdes"
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def __init__(self, device, pll, pads, mode="master"):
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assert mode in ["master", "slave"]
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if device[:4] == "xcku":
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@ -8,8 +8,10 @@ from misoc.cores.code_8b10b import Encoder, Decoder
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class S7Serdes(Module):
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def __init__(self, pll, pads, mode="master"):
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self.tx_data = Signal(32)
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self.rx_data = Signal(32)
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self.tx_k = Signal(4)
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self.tx_d = Signal(32)
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self.rx_k = Signal(4)
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self.rx_d = Signal(32)
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self.tx_idle = Signal()
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self.tx_comma = Signal()
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@ -99,10 +101,14 @@ class S7Serdes(Module):
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(0xbc)
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).Else(
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self.encoder.d[0].eq(self.tx_data[0:8]),
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self.encoder.d[1].eq(self.tx_data[8:16]),
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self.encoder.d[2].eq(self.tx_data[16:24]),
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self.encoder.d[3].eq(self.tx_data[24:32])
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self.encoder.k[0].eq(self.tx_k[0]),
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self.encoder.k[1].eq(self.tx_k[1]),
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self.encoder.k[2].eq(self.tx_k[2]),
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self.encoder.k[3].eq(self.tx_k[3]),
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self.encoder.d[0].eq(self.tx_d[0:8]),
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self.encoder.d[1].eq(self.tx_d[8:16]),
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self.encoder.d[2].eq(self.tx_d[16:24]),
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self.encoder.d[3].eq(self.tx_d[24:32])
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)
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]
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self.sync.serwb_serdes += \
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@ -213,7 +219,8 @@ class S7Serdes(Module):
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self.decoders[1].input.eq(self.rx_bitslip.o[10:20]),
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self.decoders[2].input.eq(self.rx_bitslip.o[20:30]),
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self.decoders[3].input.eq(self.rx_bitslip.o[30:40]),
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self.rx_data.eq(Cat(*[self.decoders[i].d for i in range(4)])),
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self.rx_k.eq(Cat(*[self.decoders[i].k for i in range(4)])),
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self.rx_d.eq(Cat(*[self.decoders[i].d for i in range(4)])),
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rx_idle.eq(self.rx_bitslip.o == 0),
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rx_comma.eq(((self.decoders[0].d == 0xbc) & (self.decoders[0].k == 1)) &
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((self.decoders[1].d == 0x00) & (self.decoders[1].k == 0)) &
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99
artiq/gateware/serwb/scrambler.py
Normal file
99
artiq/gateware/serwb/scrambler.py
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@ -0,0 +1,99 @@
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from functools import reduce
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from operator import xor
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from migen import *
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from misoc.interconnect import stream
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def K(x, y):
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return (y << 5) | x
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@ResetInserter()
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class _Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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flip = reduce(xor, [curval[tap] for tap in taps])
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self.comb += self.o[i].eq(flip ^ self.i[i])
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curval.insert(0, flip)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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class Scrambler(Module):
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def __init__(self, sync_interval=1024, enable=True):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
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# # #
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if enable:
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# scrambler
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scrambler = _Scrambler(32)
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self.submodules += scrambler
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self.comb += scrambler.i.eq(sink.data)
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# insert K.29.7 as sync character
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# every sync_interval cycles
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count = Signal(max=sync_interval)
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self.sync += count.eq(count + 1)
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self.comb += [
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If(count == 0,
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scrambler.reset.eq(1),
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source.stb.eq(1),
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source.k[0].eq(1),
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source.d[:8].eq(K(29, 7))
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).Else(
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb),
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source.d.eq(scrambler.o)
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)
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]
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else:
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self.comb += [
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sink.connect(source, omit={"data"}),
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source.k.eq(0b0000),
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source.d.eq(sink.data)
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]
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class Descrambler(Module):
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def __init__(self, enable=True):
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self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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if enable:
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# descrambler
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descrambler = _Scrambler(32)
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self.submodules += descrambler
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self.comb += descrambler.i.eq(sink.d)
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# detect K29.7 and synchronize descrambler
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self.comb += [
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descrambler.reset.eq(0),
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If((sink.k[0] == 1) &
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(sink.d[:8] == K(29,7)),
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sink.ack.eq(1),
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descrambler.reset.eq(1)
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).Else(
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb),
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source.data.eq(descrambler.o)
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)
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]
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else:
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self.comb += [
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sink.connect(source, omit={"d", "k"}),
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source.data.eq(sink.d)
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]
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