mirror of https://github.com/m-labs/artiq
sayma: add SYSREF sampler gateware
parent
814d0583db
commit
28fb0fd754
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@ -0,0 +1,107 @@
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from collections import namedtuple
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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class UltrascaleCRG(Module, AutoCSR):
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linerate = int(6e9)
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refclk_freq = int(150e6)
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fabric_freq = int(125e6)
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def __init__(self, platform, use_rtio_clock=False):
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self.jreset = CSRStorage(reset=1)
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self.jref = Signal()
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self.refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk2 = Signal()
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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o_O=self.refclk, o_ODIV2=refclk2),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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if use_rtio_clock:
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self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
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else:
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self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)
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jref = platform.request("dac_sysref")
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jref_se = Signal()
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self.specials += [
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Instance("IBUFDS_IBUFDISABLE",
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p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE",
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i_IBUFDISABLE=self.jreset.storage,
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i_I=jref.p, i_IB=jref.n,
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o_O=jref_se),
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# SYSREF normally meets s/h at the FPGA, except during margin
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# scan. Be paranoid and use a double-register anyway.
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MultiReg(jref_se, self.jref, "jesd")
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]
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PhyPads = namedtuple("PhyPads", "txp txn")
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class UltrascaleTX(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_pads = platform.request("dac_jesd", dac)
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phys = []
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for i in range(len(jesd_pads.txp)):
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cpll = JESD204BGTHChannelPLL(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += cpll
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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core.register_jref(jesd_crg.jref)
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# This assumes:
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# * coarse RTIO frequency = 16*SYSREF frequency
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# * JESD and coarse RTIO clocks are the same
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# (only reset may differ).
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# * SYSREF meets setup/hold at the FPGA when sampled
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# in the JESD/RTIO domain.
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#
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# Look at the 4 LSBs of the coarse RTIO timestamp counter
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# to determine SYSREF phase.
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class SysrefSampler(Module, AutoCSR):
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def __init__(self, coarse_ts, jref):
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self.sample_result = CSRStatus()
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sample = Signal()
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self.sync.rtio += If(coarse_ts[:4] == 0, sample.eq(jref))
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self.specials += MultiReg(sample, self.sample_result.status)
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@ -2,11 +2,9 @@
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import argparse
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import os
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from collections import namedtuple
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import warnings
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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@ -14,18 +12,11 @@ from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from misoc.targets.sayma_amc import BaseSoC, MiniSoC
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import serwb
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from artiq.gateware import remote_csr
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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@ -35,77 +26,10 @@ from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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PhyPads = namedtuple("PhyPads", "txp txn")
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to_jesd = ClockDomainsRenamer("jesd")
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class AD9154CRG(Module, AutoCSR):
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linerate = int(6e9)
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refclk_freq = int(150e6)
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fabric_freq = int(125e6)
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def __init__(self, platform, use_rtio_clock=False):
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self.jreset = CSRStorage(reset=1)
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self.jref = Signal()
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self.refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk2 = Signal()
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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o_O=self.refclk, o_ODIV2=refclk2),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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if use_rtio_clock:
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self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
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else:
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self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)
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jref = platform.request("dac_sysref")
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self.specials += Instance("IBUFDS_IBUFDISABLE",
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p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE",
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i_IBUFDISABLE=self.jreset.storage,
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i_I=jref.p, i_IB=jref.n,
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o_O=self.jref)
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_pads = platform.request("dac_jesd", dac)
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phys = []
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for i in range(len(jesd_pads.txp)):
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cpll = JESD204BGTHChannelPLL(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += cpll
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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self.submodules.core = core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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core.register_jref(jesd_crg.jref)
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += self.sawgs
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@ -117,7 +41,8 @@ class AD9154(Module, AutoCSR):
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class AD9154NoSAWG(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.sawgs = []
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@ -231,7 +156,7 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = AD9154CRG(platform)
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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if with_sawg:
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cls = AD9154
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else:
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@ -276,6 +201,10 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.rtio_core.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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class Master(MiniSoC, AMPSoC, RTMCommon):
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mem_map = {
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@ -433,7 +362,8 @@ class Satellite(BaseSoC, RTMCommon):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = AD9154CRG(platform, use_rtio_clock=True)
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
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platform, use_rtio_clock=True)
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if with_sawg:
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cls = AD9154
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else:
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@ -491,6 +421,10 @@ class Satellite(BaseSoC, RTMCommon):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.drtio0.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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