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suservo: fix rtio interface width
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d5eea962ec
commit
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@ -32,17 +32,18 @@ class RTServoMem(Module):
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m_state = servo.m_state.get_port(write_capable=True)
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self.specials += m_state, m_coeff
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assert w.coeff >= w.state
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assert w.state >= w.coeff
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assert len(m_coeff.dat_w) == 2*w.coeff
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assert w.coeff >= w.word
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(
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w.coeff,
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w.state,
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# coeff, profile, channel, 2 mems, rw
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3 + w.profile + w.channel + 1 + 1,
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enable_replace=False),
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rtlink.IInterface(
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w.coeff,
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w.state,
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timestamped=False)
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)
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@ -52,7 +53,6 @@ class RTServoMem(Module):
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state_sel = self.rtlink.o.address[-2]
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high_coeff = self.rtlink.o.address[0]
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self.comb += [
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self.rtlink.o.busy.eq(active),
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m_coeff.adr.eq(self.rtlink.o.address[1:]),
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m_coeff.dat_w.eq(Cat(self.rtlink.o.data, self.rtlink.o.data)),
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m_coeff.we[0].eq(self.rtlink.o.stb & ~high_coeff &
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@ -77,6 +77,7 @@ class RTServoMem(Module):
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)
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]
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self.comb += [
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self.rtlink.o.busy.eq(read),
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self.rtlink.i.stb.eq(read),
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self.rtlink.i.data.eq(Mux(state_sel,
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m_state.dat_r >> w.state - w.coeff,
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