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serwb/test: update
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@ -8,14 +8,17 @@ from artiq.gateware.serwb.phy import _SerdesMasterInit, _SerdesSlaveInit
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class SerdesModel(Module):
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def __init__(self, taps, mode="slave"):
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self.tx_idle = Signal()
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self.tx_comma = Signal()
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self.rx_idle = Signal()
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self.rx_comma = Signal()
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self.tx = Module()
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self.rx = Module()
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self.rx_bitslip_value = Signal(6)
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self.rx_delay_rst = Signal()
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self.rx_delay_inc = Signal()
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self.tx.idle = Signal()
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self.tx.comma = Signal()
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self.rx.idle = Signal()
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self.rx.comma = Signal()
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self.rx.bitslip_value = Signal(6)
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self.rx.delay_rst = Signal()
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self.rx.delay_inc = Signal()
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self.valid_bitslip = Signal(6)
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self.valid_delays = Signal(taps)
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@ -30,29 +33,29 @@ class SerdesModel(Module):
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self.comb += valid_delays[taps-1-i].eq(self.valid_delays[i])
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self.sync += [
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bitslip.eq(self.rx_bitslip_value),
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If(self.rx_delay_rst,
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bitslip.eq(self.rx.bitslip_value),
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If(self.rx.delay_rst,
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delay.eq(0)
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).Elif(self.rx_delay_inc,
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).Elif(self.rx.delay_inc,
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delay.eq(delay + 1)
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)
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]
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if mode == "master":
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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self.comb += self.fsm.reset.eq(self.tx_idle)
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self.comb += self.fsm.reset.eq(self.tx.idle)
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fsm.act("IDLE",
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If(self.tx_comma,
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If(self.tx.comma,
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NextState("SEND_COMMA")
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),
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self.rx_idle.eq(1)
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self.rx.idle.eq(1)
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)
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fsm.act("SEND_COMMA",
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If(valid_delays[delay] &
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(bitslip == self.valid_bitslip),
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self.rx_comma.eq(1)
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self.rx.comma.eq(1)
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),
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If(~self.tx_comma,
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If(~self.tx.comma,
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NextState("READY")
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)
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)
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@ -60,15 +63,15 @@ class SerdesModel(Module):
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elif mode == "slave":
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.rx_idle.eq(1),
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self.rx.idle.eq(1),
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NextState("SEND_COMMA")
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)
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fsm.act("SEND_COMMA",
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If(valid_delays[delay] &
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(bitslip == self.valid_bitslip),
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self.rx_comma.eq(1)
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self.rx.comma.eq(1)
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),
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If(~self.tx_idle,
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If(~self.tx.idle,
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NextState("READY")
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)
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)
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