M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

drtio: print diagnostic info on satellite write underflow (#947)

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2018-03-12 23:41:19 +08:00
parent eb6e59b44c
commit 1d081ed6c2
3 changed files with 33 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
artiq/firmware/satman/main.rs
View File

@ -177,7 +177,6 @@ fn process_errors() {
let errors;
unsafe {
errors = (csr::DRTIO[0].protocol_error_read)();
(csr::DRTIO[0].protocol_error_write)(errors);
}
if errors & 1 != 0 {
error!("received packet of an unknown type");
@ -186,11 +185,23 @@ fn process_errors() {
error!("received truncated packet");
}
if errors & 4 != 0 {
error!("write underflow");
let channel;
let timestamp_event;
let timestamp_counter;
unsafe {
channel = (csr::DRTIO[0].underflow_channel_read)();
timestamp_event = (csr::DRTIO[0].underflow_timestamp_event_read)() as i64;
timestamp_counter = (csr::DRTIO[0].underflow_timestamp_counter_read)() as i64;
}
error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
}
if errors & 8 != 0 {
error!("write overflow");
}
unsafe {
(csr::DRTIO[0].protocol_error_write)(errors);
}
}
#[cfg(rtio_frequency = "150.0")]

17
artiq/gateware/drtio/rt_errors_satellite.py
View File

@ -9,6 +9,10 @@ from artiq.gateware.rtio.cdc import BlindTransfer
class RTErrorsSatellite(Module, AutoCSR):
def __init__(self, rt_packet, outputs):
self.protocol_error = CSR(4)
self.underflow_channel = CSRStatus(16)
self.underflow_timestamp_event = CSRStatus(64)
self.underflow_timestamp_counter = CSRStatus(64)
self.rtio_error = CSR(3)
self.sequence_error_channel = CSRStatus(16)
self.collision_channel = CSRStatus(16)
@ -49,16 +53,25 @@ class RTErrorsSatellite(Module, AutoCSR):
# internal ARTIQ bugs.
underflow = Signal()
overflow = Signal()
underflow_error_cri = Signal(16+64+64)
underflow_error_csr = Signal(16+64+64)
self.comb += [
underflow.eq(outputs.cri.o_status[1]),
overflow.eq(outputs.cri.o_status[0])
overflow.eq(outputs.cri.o_status[0]),
underflow_error_cri.eq(Cat(outputs.cri.chan_sel[:16],
outputs.cri.timestamp,
outputs.cri.counter)),
Cat(self.underflow_channel.status,
self.underflow_timestamp_event.status,
self.underflow_timestamp_counter.status).eq(underflow_error_csr)
]
error_csr(self.protocol_error,
(rt_packet.unknown_packet_type, False, None, None),
(rt_packet.packet_truncated, False, None, None),
(underflow, True, None, None),
(underflow, True, underflow_error_cri, underflow_error_csr),
(overflow, True, None, None)
)
error_csr(self.rtio_error,
(outputs.sequence_error, False,
outputs.sequence_error_channel, self.sequence_error_channel.status),

6
artiq/gateware/test/drtio/test_full_stack.py
View File

@ -222,11 +222,15 @@ class TestFullStack(unittest.TestCase):
self.assertEqual(errors, 0)
yield from csrs.underflow_margin.write(0)
tb.delay(100)
yield from tb.write(0, 1)
yield from tb.write(42, 1)
for i in range(12):
yield
errors = yield from saterr.protocol_error.read()
underflow_channel = yield from saterr.underflow_channel.read()
underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read()
self.assertEqual(errors, 4) # write underflow
self.assertEqual(underflow_channel, 42)
self.assertEqual(underflow_timestamp_event, 100)
yield from saterr.protocol_error.write(errors)
yield
errors = yield from saterr.protocol_error.read()