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sayma/serwb: adapt, full reset of rtm on link reset

This commit is contained in:
Florent Kermarrec 2018-04-17 19:22:09 +02:00
parent 8edf4541d6
commit 439d2bf2bc
2 changed files with 12 additions and 8 deletions
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4
artiq/gateware/targets/sayma_amc.py
View File

@ -170,11 +170,11 @@ class Standalone(MiniSoC, AMPSoC):
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master", phy_width=4)
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc")
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave")
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)

16
artiq/gateware/targets/sayma_rtm.py
View File

@ -26,6 +26,7 @@ class CRG(Module):
self.clock_domains.cd_clk200 = ClockDomain()
self.serwb_refclk = Signal()
self.serwb_reset = Signal()
pll_locked = Signal()
pll_fb = Signal()
@ -53,9 +54,9 @@ class CRG(Module):
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked)
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.serwb_reset),
AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked | self.serwb_reset),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.serwb_reset)
]
reset_counter = Signal(4, reset=15)
@ -156,12 +157,15 @@ class SaymaRTM(Module):
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 10.)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave", phy_width=4)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk),
self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
]
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb