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kasli: add tester target
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187
artiq/examples/kasli_basic/device_db_tester.py
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187
artiq/examples/kasli_basic/device_db_tester.py
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@ -0,0 +1,187 @@
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core_addr = "kasli-2.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"i2c_switch0": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe0}
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},
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"i2c_switch1": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe2}
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},
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}
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for i in range(8):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut" if i < 4 else "TTLOut",
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"arguments": {"channel": i},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 8}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 9}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 10}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 11}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 12}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 13}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 125e6,
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"clk_sel": 0
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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}
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}
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device_db["spi_sampler0_adc"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 14}
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}
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device_db["spi_sampler0_pgia"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 15}
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}
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device_db["spi_sampler0_cnv"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 16},
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}
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device_db["sampler0"] = {
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"type": "local",
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"module": "artiq.coredevice.sampler",
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"class": "Sampler",
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"arguments": {
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"spi_adc_device": "spi_sampler0_adc",
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"spi_pgia_device": "spi_sampler0_pgia",
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"cnv_device": "spi_sampler0_cnv"
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}
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}
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device_db["spi_zotino0"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 17}
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}
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device_db["ttl_zotino0_ldac"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 18}
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}
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device_db["ttl_zotino0_clr"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 19}
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}
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device_db["zotino0"] = {
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"type": "local",
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"module": "artiq.coredevice.zotino",
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"class": "Zotino",
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"arguments": {
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"spi_device": "spi_zotino0",
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"ldac_device": "ttl_zotino0_ldac",
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"clr_device": "ttl_zotino0_clr"
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}
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}
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device_db.update(
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led0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 20}
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},
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led1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 21}
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},
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)
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@ -269,7 +269,7 @@ def main():
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"kasli": {
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"programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"),
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"variants": ["opticlock", "suservo", "sysu", "mitll", "ustc",
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"master", "satellite"],
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"tester", "master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0x400000),
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"storage": ("spi0", 0x440000),
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@ -787,6 +787,101 @@ class USTC(_StandaloneBase):
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self.add_rtio(rtio_channels)
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class Tester(_StandaloneBase):
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"""
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Configuration for CI tests. Contains the maximum number of different EEMs.
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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platform = self.platform
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platform.add_extension(_urukul("eem1", "eem0"))
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platform.add_extension(_sampler("eem3", "eem2"))
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platform.add_extension(_zotino("eem4"))
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platform.add_extension(_dio("eem5"))
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try:
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# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
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self.comb += platform.request("clk_sel").eq(1)
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except ConstraintError:
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pass
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# EEM5: TTL
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rtio_channels = []
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for i in range(8):
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pads = platform.request("eem5", i)
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if i < 4:
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cls = ttl_serdes_7series.InOut_8X
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else:
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cls = ttl_serdes_7series.Output_8X
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phy = cls(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM0, EEM1: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
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self.platform.request("eem1_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem1_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem1_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM2, EEM3: Sampler
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phy = spi2.SPIMaster(self.platform.request("eem3_adc_spi_p"),
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self.platform.request("eem3_adc_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
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self.platform.request("eem3_pgia_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem3_cnv")
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sdr = platform.request("eem3_sdr")
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self.specials += DifferentialOutput(1, sdr.p, sdr.n)
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# EEM4: Zotino
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phy = spi2.SPIMaster(self.platform.request("eem4_spi_p"),
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self.platform.request("eem4_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for signal in "ldac_n clr_n".split():
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pads = platform.request("eem4_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp_ctl = platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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print(len(rtio_channels))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class _RTIOClockMultiplier(Module):
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def __init__(self, rtio_clk_freq):
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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@ -1098,7 +1193,7 @@ def main():
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock/suservo/sysu/mitll/ustc/"
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"master/satellite "
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"tester/master/satellite "
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"(default: %(default)s)")
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args = parser.parse_args()
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@ -1113,6 +1208,8 @@ def main():
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cls = MITLL
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elif variant == "ustc":
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cls = USTC
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elif variant == "tester":
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cls = Tester
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elif variant == "master":
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cls = Master
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elif variant == "satellite":
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