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drtio: increase default underflow margin. Closes #947

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This commit is contained in:
Sebastien Bourdeauducq 2018-03-09 00:49:07 +08:00
parent 37f5f0d38d
commit e38187c760
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/rt_controller_master.py
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@ -19,7 +19,7 @@ class _CSRs(AutoCSR):
self.tsc_correction = CSRStorage(64)
self.set_time = CSR()
self.underflow_margin = CSRStorage(16, reset=200)
self.underflow_margin = CSRStorage(16, reset=300)
self.o_get_buffer_space = CSR()
self.o_dbg_buffer_space = CSRStatus(16)