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targets/sayma: adapt to new serwb clocking
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3248caa184
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aef0153a8f
@ -169,22 +169,11 @@ class Standalone(MiniSoC, AMPSoC):
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self.config["SLAVE_FPGA_GATEWARE"] = 0x150000
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)
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self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
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self.submodules += serwb_pll
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="master")
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serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master")
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_amc.serdes.cd_serwb_serdes.clk,
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serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk)
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serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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@ -21,35 +21,48 @@ from artiq import __version__ as artiq_version
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class CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys0p2x = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_clk200 = ClockDomain()
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clk50 = platform.request("clk50")
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self.reset = Signal()
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self.serwb_refclk = Signal()
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys0p2x = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=20.0,
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p_CLKFBOUT_MULT=20, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk50, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=self.serwb_refclk, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 25MHz
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p_CLKOUT0_DIVIDE=40, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys0p2x,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys,
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# 500MHz
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_sys4x,
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# 200MHz
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p_CLKOUT3_DIVIDE=5, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200
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),
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Instance("BUFG", i_I=pll_sys0p2x, o_O=self.cd_sys0p2x.clk),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.reset),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.reset)
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AsyncResetSynchronizer(self.cd_sys0p2x, ~pll_locked),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked)
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]
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reset_counter = Signal(4, reset=15)
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@ -148,23 +161,13 @@ class SaymaRTM(Module):
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self.comb += platform.request("hmc7043_reset").eq(0)
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(62.5e6, 625e6, vco_div=1)
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self.submodules += serwb_pll
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 16.)
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platform.add_period_constraint(serwb_pads.clk_p, 10.)
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serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)
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self.comb += self.crg.serwb_refclk.eq(serwb_phy.serdes.refclk)
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csr_devices.append("serwb_phy_rtm")
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
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serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk)
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serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
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self.submodules += serwb_core
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