spi2: reset configuration in rio_phy

2024-12-25 03:08:27 +08:00 · 2018-03-07 14:23:28 +00:00 · 2018-03-07 14:23:28 +00:00 · b0282fa855
commit b0282fa855
parent 7afb23e8be
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/phy/spi2.py
+++ b/artiq/gateware/rtio/phy/spi2.py
@ -73,7 +73,7 @@ class SPIMaster(Module):
        config.end.reset = 1
        read = Signal()

-        self.sync.rio += [
+        self.sync.rio_phy += [
            If(self.rtlink.i.stb,
                read.eq(0)
            ),