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artiq
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jesd204: use separate controls for reset and input buffer disable

pull/1082/head
Sebastien Bourdeauducq 2018-06-22 11:38:18 +08:00
parent d9955fee76
commit 76fc63bbf7
2 changed files with 5 additions and 3 deletions
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3
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -36,7 +36,8 @@ fn read(addr: u16) -> u8 {
fn jesd_unreset() {
unsafe {
csr::ad9154_crg::jreset_write(0)
csr::ad9154_crg::ibuf_disable_write(0);
csr::ad9154_crg::jreset_write(0);
}
}

5
artiq/gateware/jesd204_tools.py
View File

@ -20,6 +20,7 @@ class UltrascaleCRG(Module, AutoCSR):
fabric_freq = int(125e6)
def __init__(self, platform, use_rtio_clock=False):
self.ibuf_disable = CSRStorage(reset=1)
self.jreset = CSRStorage(reset=1)
self.jref = Signal()
self.refclk = Signal()
@ -29,7 +30,7 @@ class UltrascaleCRG(Module, AutoCSR):
refclk_pads = platform.request("dac_refclk", 1)
platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
self.specials += [
Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00,
Instance("IBUFDS_GTE3", i_CEB=self.ibuf_disable.storage, p_REFCLK_HROW_CK_SEL=0b00,
i_I=refclk_pads.p, i_IB=refclk_pads.n,
o_O=self.refclk, o_ODIV2=refclk2),
AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
@ -46,7 +47,7 @@ class UltrascaleCRG(Module, AutoCSR):
self.specials += [
Instance("IBUFDS_IBUFDISABLE",
p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE",
i_IBUFDISABLE=self.jreset.storage,
i_IBUFDISABLE=self.ibuf_disable.storage,
i_I=jref.p, i_IB=jref.n,
o_O=jref_se),
# SYSREF normally meets s/h at the FPGA, except during margin