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artiq/gateware/test/suservo/__init__.py
Normal file
0
artiq/gateware/test/suservo/__init__.py
Normal file
165
artiq/gateware/test/suservo/test_adc.py
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165
artiq/gateware/test/suservo/test_adc.py
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import logging
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import string
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import unittest
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from migen import *
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from migen.genlib import io
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from artiq.gateware.suservo.adc_ser import ADC, ADCParams
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class DDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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do_clk0 = Signal(reset_less=True)
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do_j1 = Signal(reset_less=True)
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do_j2 = Signal(reset_less=True)
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do_j3 = Signal(reset_less=True)
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self.sync.async += [
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do_clk0.eq(clk),
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do_j1.eq(i1),
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do_j2.eq(i2),
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If(Cat(do_clk0, clk) == 0b10,
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o.eq(do_j1),
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do_j3.eq(do_j2),
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).Elif(Cat(do_clk0, clk) == 0b01,
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o.eq(do_j3),
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)
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]
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class DDROutput:
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@staticmethod
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def lower(dr):
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return DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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class DDRInputImpl(Module):
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def __init__(self, i, o1, o2, clk):
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di_clk0 = Signal(reset_less=True)
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# SAME_EDGE_PIPELINED is effectively one register for o1
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# (during rising clock)
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di_j1 = Signal(reset_less=True)
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di_j2 = Signal(reset_less=True)
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di_j3 = Signal(reset_less=True)
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self.sync.async += [
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di_clk0.eq(clk),
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di_j1.eq(i),
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If(Cat(di_clk0, clk) == 0b10,
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di_j3.eq(di_j1),
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o1.eq(di_j3),
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o2.eq(di_j2)
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).Elif(Cat(di_clk0, clk) == 0b01,
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di_j2.eq(di_j1)
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)
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]
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class DDRInput:
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@staticmethod
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def lower(dr):
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return DDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
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class TB(Module):
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def __init__(self, params):
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self.params = p = params
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self.sck = Signal()
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self.clkout = Signal(reset_less=True)
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self.cnv_b = Signal()
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self.sck_en = Signal()
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self.sck_en_ret = Signal()
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adc_sck_en = Signal()
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cd_adc = ClockDomain("adc", reset_less=True)
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self.clock_domains += cd_adc
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self.sdo = []
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self.data = [Signal((p.width, True), reset_less=True)
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for i in range(p.channels)]
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srs = []
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for i in range(p.lanes):
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name = "sdo" + string.ascii_lowercase[i]
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sdo = Signal(name=name, reset_less=True)
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self.sdo.append(sdo)
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setattr(self, name, sdo)
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sr = Signal(p.width*p.channels//p.lanes, reset_less=True)
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srs.append(sr)
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self.specials += io.DDROutput(
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# one for async
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self._dly(sr[-1], -1), self._dly(sr[-2], -1), sdo)
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self.sync.adc += [
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If(adc_sck_en,
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sr[2:].eq(sr)
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)
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]
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cnv_b_old = Signal(reset_less=True)
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self.sync.async += [
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cnv_b_old.eq(self.cnv_b),
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If(Cat(cnv_b_old, self.cnv_b) == 0b10,
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sr.eq(Cat(reversed(self.data[2*i:2*i + 2]))),
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)
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]
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adc_clk_rec = Signal()
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self.comb += [
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adc_sck_en.eq(self._dly(self.sck_en, 1)),
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self.sck_en_ret.eq(self._dly(adc_sck_en)),
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adc_clk_rec.eq(self._dly(self.sck, 1)),
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self.clkout.eq(self._dly(adc_clk_rec)),
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]
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def _dly(self, sig, n=0):
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n += self.params.t_rtt*4//2 # t_{sys,adc,ret}/t_async half rtt
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dly = Signal(n, reset_less=True)
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self.sync.async += dly.eq(Cat(sig, dly))
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return dly[-1]
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def main():
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params = ADCParams(width=8, channels=4, lanes=2,
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t_cnvh=3, t_conv=5, t_rtt=4)
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tb = TB(params)
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adc = ADC(tb, params)
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tb.submodules += adc
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def run(tb):
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dut = adc
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for i, ch in enumerate(tb.data):
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yield ch.eq(i)
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assert (yield dut.done)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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yield
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assert not (yield dut.done)
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while not (yield dut.done):
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yield
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x = (yield from [(yield d) for d in dut.data])
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for i, ch in enumerate(x):
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assert ch == i, (hex(ch), hex(i))
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run_simulation(tb, [run(tb)],
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vcd_name="adc.vcd",
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clocks={
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"sys": (8, 0),
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"adc": (8, 0),
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"ret": (8, 0),
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"async": (2, 0),
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},
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special_overrides={
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io.DDROutput: DDROutput,
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io.DDRInput: DDRInput
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})
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class ADCTest(unittest.TestCase):
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def test_run(self):
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main()
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if __name__ == "__main__":
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logging.basicConfig(level=logging.DEBUG)
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main()
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93
artiq/gateware/test/suservo/test_dds.py
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93
artiq/gateware/test/suservo/test_dds.py
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import logging
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import unittest
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from migen import *
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from artiq.gateware.suservo.dds_ser import DDSParams, DDS
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class TB(Module):
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def __init__(self, p):
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self.cs_n = Signal()
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self.clk = Signal()
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self.mosi = [Signal() for i in range(p.channels)]
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for i, m in enumerate(self.mosi):
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setattr(self, "mosi{}".format(i), m)
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self.miso = Signal()
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self.io_update = Signal()
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clk0 = Signal()
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self.sync += clk0.eq(self.clk)
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sample = Signal()
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self.comb += sample.eq(Cat(self.clk, clk0) == 0b01)
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self.ddss = []
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for i in range(p.channels):
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dds = Record([("ftw", 32), ("pow", 16), ("asf", 16), ("cmd", 8)])
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sr = Signal(len(dds))
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self.sync += [
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If(~self.cs_n & sample,
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sr.eq(Cat(self.mosi[i], sr))
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),
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If(self.io_update,
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dds.raw_bits().eq(sr)
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)
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]
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self.ddss.append(dds)
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@passive
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def log(self, data):
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i = 0
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while True:
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i += 1
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if (yield self.io_update):
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yield
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dat = []
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for dds in self.ddss:
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v = yield from [(yield getattr(dds, k))
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for k in "cmd ftw pow asf".split()]
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dat.append(v)
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data.append((i, dat))
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else:
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yield
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def main():
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p = DDSParams(channels=4, width=8 + 32 + 16 + 16, clk=1)
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tb = TB(p)
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dds = DDS(tb, p)
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tb.submodules += dds
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def run(tb):
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dut = dds
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for i, ch in enumerate(dut.profile):
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yield ch.eq((((0
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<< 16 | i | 0x20)
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<< 16 | i | 0x30)
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<< 32 | i | 0x40))
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# assert (yield dut.done)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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yield
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yield
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assert not (yield dut.done)
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while not (yield dut.done):
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yield
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yield
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data = []
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run_simulation(tb, [tb.log(data), run(tb)], vcd_name="dds.vcd")
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assert data[-1][1] == [[0xe, 0x40 | i, 0x30 | i, 0x20 | i] for i in
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range(4)]
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class DDSTest(unittest.TestCase):
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def test_run(self):
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main()
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if __name__ == "__main__":
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logging.basicConfig(level=logging.DEBUG)
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main()
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56
artiq/gateware/test/suservo/test_iir.py
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56
artiq/gateware/test/suservo/test_iir.py
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@ -0,0 +1,56 @@
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import logging
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import unittest
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from migen import *
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from artiq.gateware.suservo import iir
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def main():
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w_kasli = iir.IIRWidths(state=25, coeff=18, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=3, profile=5)
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w = iir.IIRWidths(state=17, coeff=16, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=2, profile=1)
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def run(dut):
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for i, ch in enumerate(dut.adc):
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yield ch.eq(i)
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for i, ch in enumerate(dut.ctrl):
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yield ch.en_iir.eq(1)
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yield ch.en_out.eq(1)
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yield ch.profile.eq(i)
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for i in range(1 << w.channel):
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yield from dut.set_state(i, i << 8, coeff="x1")
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yield from dut.set_state(i, i << 8, coeff="x0")
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for j in range(1 << w.profile):
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yield from dut.set_state(i,
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(j << 1) | (i << 8), profile=j, coeff="y1")
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for k, l in enumerate("pow offset ftw0 ftw1".split()):
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yield from dut.set_coeff(i, profile=j, coeff=l,
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value=(i << 12) | (j << 8) | (k << 4))
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yield
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for i in range(1 << w.channel):
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for j in range(1 << w.profile):
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for k, l in enumerate("cfg a1 b0 b1".split()):
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yield from dut.set_coeff(i, profile=j, coeff=l,
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value=(i << 12) | (j << 8) | (k << 4))
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yield from dut.set_coeff(i, profile=j, coeff="cfg",
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value=(i << 0) | (j << 8)) # sel, dly
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yield
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for i in range(10):
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yield from dut.check_iter()
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yield
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dut = iir.IIR(w)
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run_simulation(dut, [run(dut)], vcd_name="iir.vcd")
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class IIRTest(unittest.TestCase):
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def test_run(self):
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main()
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if __name__ == "__main__":
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logging.basicConfig(level=logging.DEBUG)
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main()
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109
artiq/gateware/test/suservo/test_servo.py
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109
artiq/gateware/test/suservo/test_servo.py
Normal file
@ -0,0 +1,109 @@
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import logging
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import unittest
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from migen import *
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from migen.genlib import io
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from artiq.gateware.test.suservo import test_adc, test_dds
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from artiq.gateware.suservo import servo
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class ServoSim(servo.Servo):
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def __init__(self):
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adc_p = servo.ADCParams(width=16, channels=8, lanes=4,
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t_cnvh=4, t_conv=57, t_rtt=4)
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iir_p = servo.IIRWidths(state=25, coeff=18, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=3, profile=5)
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dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
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channels=adc_p.channels, clk=1)
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self.submodules.adc_tb = test_adc.TB(adc_p)
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self.submodules.dds_tb = test_dds.TB(dds_p)
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servo.Servo.__init__(self, self.adc_tb, self.dds_tb,
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adc_p, iir_p, dds_p)
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def test(self):
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assert (yield self.done)
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adc = 1
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x0 = 0x0141
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yield self.adc_tb.data[adc].eq(x0)
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channel = 3
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yield self.iir.adc[channel].eq(adc)
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yield self.iir.ctrl[channel].en_iir.eq(1)
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yield self.iir.ctrl[channel].en_out.eq(1)
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profile = 5
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yield self.iir.ctrl[channel].profile.eq(profile)
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x1 = 0x0743
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yield from self.iir.set_state(adc, x1, coeff="x1")
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y1 = 0x1145
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yield from self.iir.set_state(channel, y1,
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profile=profile, coeff="y1")
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coeff = dict(pow=0x1333, offset=0x1531, ftw0=0x1727, ftw1=0x1929,
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a1=0x0135, b0=0x0337, b1=0x0539, cfg=adc | (0 << 3))
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for ks in "pow offset ftw0 ftw1", "a1 b0 b1 cfg":
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for k in ks.split():
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yield from self.iir.set_coeff(channel, value=coeff[k],
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profile=profile, coeff=k)
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yield
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yield self.start.eq(1)
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yield
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yield self.start.eq(0)
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while not (yield self.dds_tb.io_update):
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yield
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yield # io_update
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w = self.iir.widths
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x0 = x0 << (w.state - w.adc - 1)
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_ = yield from self.iir.get_state(adc, coeff="x1")
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assert _ == x0, (hex(_), hex(x0))
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offset = coeff["offset"] << (w.state - w.coeff - 1)
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a1, b0, b1 = coeff["a1"], coeff["b0"], coeff["b1"]
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out = (
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0*(1 << w.shift - 1) + # rounding
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a1*(0 - y1) + b0*(offset - x0) + b1*(offset - x1)
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) >> w.shift
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y1 = min(max(0, out), (1 << w.state - 1) - 1)
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_ = yield from self.iir.get_state(channel, profile, coeff="y1")
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assert _ == y1, (hex(_), hex(y1))
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_ = yield self.dds_tb.ddss[channel].ftw
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ftw = (coeff["ftw1"] << 16) | coeff["ftw0"]
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assert _ == ftw, (hex(_), hex(ftw))
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_ = yield self.dds_tb.ddss[channel].pow
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assert _ == coeff["pow"], (hex(_), hex(coeff["pow"]))
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_ = yield self.dds_tb.ddss[channel].asf
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asf = y1 >> (w.state - w.asf - 1)
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assert _ == asf, (hex(_), hex(asf))
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def main():
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servo = ServoSim()
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run_simulation(servo, servo.test(), vcd_name="servo.vcd",
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clocks={
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"sys": (8, 0),
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"adc": (8, 0),
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"ret": (8, 0),
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"async": (2, 0),
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},
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special_overrides={
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io.DDROutput: test_adc.DDROutput,
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io.DDRInput: test_adc.DDRInput
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})
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class ServoTest(unittest.TestCase):
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def test_run(self):
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main()
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if __name__ == "__main__":
|
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main()
|
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