mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
serwb: replace valid/ready with stb/ack
This commit is contained in:
parent
c8a08375f8
commit
1fd96eb0fd
@ -33,16 +33,16 @@ class SERWBCore(Module):
|
||||
packetizer.source.connect(tx_fifo.sink),
|
||||
tx_fifo.source.connect(scrambler.sink),
|
||||
If(phy.init.ready,
|
||||
If(scrambler.source.valid,
|
||||
If(scrambler.source.stb,
|
||||
phy.serdes.tx_k.eq(scrambler.source.k),
|
||||
phy.serdes.tx_d.eq(scrambler.source.d)
|
||||
),
|
||||
scrambler.source.ready.eq(phy.serdes.tx_ce)
|
||||
scrambler.source.ack.eq(phy.serdes.tx_ce)
|
||||
),
|
||||
|
||||
# phy --> core
|
||||
If(phy.init.ready,
|
||||
descrambler.sink.valid.eq(phy.serdes.rx_ce),
|
||||
descrambler.sink.stb.eq(phy.serdes.rx_ce),
|
||||
descrambler.sink.k.eq(phy.serdes.rx_k),
|
||||
descrambler.sink.d.eq(phy.serdes.rx_d)
|
||||
),
|
||||
|
Loading…
Reference in New Issue
Block a user