M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio/sed: min_space → buffer_space

This commit is contained in:
Sebastien Bourdeauducq 2017-09-21 14:36:13 +08:00
parent d8aa75b742
commit 07d3f87c51
2 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/rtio/sed/core.py
View File

@ -13,7 +13,7 @@ __all__ = ["SED"]
class SED(Module):
def __init__(self, channels, glbl_fine_ts_width, mode,
lane_count=8, fifo_depth=128, enable_spread=True,
quash_channels=[], interface=None, report_min_space=False):
quash_channels=[], interface=None, report_buffer_space=False):
if mode == "sync":
lane_dist_cdr = lambda x: x
fifos_cdr = lambda x: x
@ -37,7 +37,7 @@ class SED(Module):
interface=interface))
self.submodules.fifos = fifos_cdr(
FIFOs(lane_count, fifo_depth,
layouts.fifo_payload(channels), mode, report_min_space))
layouts.fifo_payload(channels), mode, report_buffer_space))
self.submodules.gates = gates_cdr(
Gates(lane_count, seqn_width,
layouts.fifo_payload(channels),
@ -52,8 +52,8 @@ class SED(Module):
for o, i in zip(self.gates.output, self.output_driver.input):
self.comb += i.eq(o)
if report_min_space:
self.comb += self.cri.o_buffer_space.eq(self.fifos.min_space)
if report_buffer_space:
self.comb += self.cri.o_buffer_space.eq(self.fifos.buffer_space)
@property
def cri(self):

10
artiq/gateware/rtio/sed/fifos.py
View File

@ -11,15 +11,15 @@ __all__ = ["FIFOs"]
class FIFOs(Module):
def __init__(self, lane_count, fifo_depth, layout_payload, mode, report_min_space=False):
def __init__(self, lane_count, fifo_depth, layout_payload, mode, report_buffer_space=False):
seqn_width = layouts.seqn_width(lane_count, fifo_depth)
self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
for _ in range(lane_count)]
self.output = [Record(layouts.fifo_egress(seqn_width, layout_payload))
for _ in range(lane_count)]
if report_min_space:
self.min_space = Signal(max=fifo_depth+1)
if report_buffer_space:
self.buffer_space = Signal(max=fifo_depth+1)
# # #
@ -46,7 +46,7 @@ class FIFOs(Module):
fifo.re.eq(output.re)
]
if report_min_space:
if report_buffer_space:
if mode != "sync":
raise NotImplementedError
@ -81,4 +81,4 @@ class FIFOs(Module):
max_level_valid_counter.eq(max_level_valid_counter - 1)
)
]
self.comb += If(max_level_valid, self.min_space.eq(fifo_depth - max_level))
self.comb += If(max_level_valid, self.buffer_space.eq(fifo_depth - max_level))