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1563 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 560849e693 sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware 2019-03-23 13:41:22 +08:00
Sebastien Bourdeauducq bbb8c00518 sayma_amc: default to satellite variant 2019-03-23 13:37:55 +08:00
Sebastien Bourdeauducq 18fbe0b081 sayma_rtm_drtio: support v2 hardware 2019-03-23 13:31:28 +08:00
Sebastien Bourdeauducq c7205ad82f sayma_rtm: preliminary v2 support 2019-03-23 12:37:03 +08:00
Sebastien Bourdeauducq 33b28f6e56 sayma_amc: add placeholder code to use DDMTD signals on v2 hardware 2019-03-21 17:37:22 +08:00
Sebastien Bourdeauducq 2ec5a58c59 sayma_amc: si5324_clkout -> cdr_clk_clean 2019-03-21 14:09:33 +08:00
Sebastien Bourdeauducq e47ba4b35e kasli_generic: fix identifier string 2019-03-08 19:57:20 +08:00
Sebastien Bourdeauducq 62c7f75a9e sayma_amc: support hardware revisions 2019-02-25 23:49:45 +08:00
Sebastien Bourdeauducq d45249197c siphaser: improve ultrascale clock routing 2019-02-25 23:00:01 +08:00
Sebastien Bourdeauducq de3992bbdd kasli: remove HUST variants (supported by kasli_generic) 2019-02-23 15:44:17 +08:00
Sebastien Bourdeauducq 791f830ef6 kasli_generic: support DRTIO 2019-02-23 15:41:05 +08:00
Sebastien Bourdeauducq 1c35c051a5 kasli: remove variants supported by generic builder 2019-02-22 23:08:49 +08:00
Sebastien Bourdeauducq 8edc2318ab style 2019-02-22 17:19:20 +08:00
Sebastien Bourdeauducq 6ad2e13515 kasli: add generic builder (WIP) 2019-02-12 19:18:09 +08:00
Sebastien Bourdeauducq ff4e4f15ed kasli: expose base SoC classes 2019-02-12 18:33:27 +08:00
Sebastien Bourdeauducq 1cfd26dc2e kasli: add UNSW variant 2019-02-08 17:51:51 +08:00
Sebastien Bourdeauducq 3e8fe3f29d suservo: fix permissions 2019-02-08 14:54:02 +08:00
hartytp 87e85bcc14 suservo: fix coefficient data writing 
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
 2019-02-07 14:47:11 +01:00
Sebastien Bourdeauducq b56c7cec1e kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target 
Urukul sync is not reliable at 125/1000
 2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq ea431b6982 sayma_rtm: use 150MHz RTIO freq for DDMTD 2019-01-31 20:43:44 +08:00
Sebastien Bourdeauducq ec230d6560 sayma: move SYSREF DDMTD to the RTM 
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
 2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq 8119000982 sayma_rtm_drtio: use Si5324 soft reset 
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.

Allows using Si5324 + HMC7043 chips at the same time.

Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
 2019-01-31 19:43:54 +08:00
Sebastien Bourdeauducq d3c608aaec jesd204sync: reset and check lock status of DDMTD helper PLL in firmware 2019-01-31 15:11:16 +08:00
Sebastien Bourdeauducq c591009220 sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler 
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
 2019-01-29 23:30:01 +08:00
Sebastien Bourdeauducq 9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq 47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq 443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq 81b0046f98 ddmtd: add deglitchers 2019-01-27 20:38:41 +08:00
Sebastien Bourdeauducq 8632b553d2 ddmtd: use IOB register to sample input 2019-01-27 09:50:02 +08:00
Sebastien Bourdeauducq 9966e789fc sayma: simplify Ultrascale LVDS T false path 
Recommended by Xilinx.
 2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq 359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq cb04230f86 sayma: SYSREF setup/hold validation demonstration 
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
 2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq 3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) 
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
 2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq 07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq 154269b77a kasli: fix HUST satellite Urukul 2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq d7e6f104d2 kasli: add HUST variants 2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq 81f2b2c864 kasli: remove unpopulated Tester EEMs 
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
 2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq 9ee5fea88d kasli: support optional SATA port for DRTIO 2019-01-22 18:06:48 +08:00
Sebastien Bourdeauducq bff8c8cb05 kasli: add Berkeley variant 2019-01-21 17:44:17 +08:00
Sebastien Bourdeauducq a2ff2cc173 sayma_amc: use more selective IOBUFDS false path 2019-01-19 11:47:50 +08:00
David Nadlinger 1c71ae636a examples: Add edge counters to kasli_tester variant 
This enables test_edge_counter on the CI system.
 2019-01-15 10:55:07 +00:00
David Nadlinger a565f77538 Add gateware input event counter 2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq 4cb9f77fd8 sayma_amc: fix Master timing constraints 2019-01-13 13:53:07 +08:00
Sebastien Bourdeauducq 9b213b17af sayma_amc: forward RTM UART in Master variant as well 2019-01-09 18:57:57 +08:00
Sebastien Bourdeauducq c7b18952b8 sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad 2019-01-09 13:47:08 +08:00
Sebastien Bourdeauducq 3217488824 add Sayma RTM DRTIO target 2019-01-07 00:13:47 +08:00
Sebastien Bourdeauducq 66b3132c28 sayma_amc: fix RTIO TSC instantiation 2019-01-06 14:54:32 +08:00
Sebastien Bourdeauducq cf9447ab77 rtio/cri: remove unneeded CSR management 2019-01-05 23:40:45 +08:00
Sebastien Bourdeauducq 2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Sebastien Bourdeauducq 62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq 0972d61e81 ttl_serdes_ultrascale: use GTH clock domains 2019-01-03 20:50:04 +08:00
Sebastien Bourdeauducq f007895fad drtio/gth_ultrascale: fix rtiox clock domain 2019-01-03 20:49:38 +08:00
Sebastien Bourdeauducq 10ebf63c47 jesd204_tools: get the Vivado timing analyzer to behave 2019-01-03 20:22:35 +08:00
Sebastien Bourdeauducq 4af8fd6a0d ttl_serdes_ultrascale: fix Input 2019-01-03 20:14:54 +08:00
Sebastien Bourdeauducq 175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq 77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Robert Jördens 6df4ae934f eem: name the servo submodule 
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos

close #1201

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 11:36:40 +01:00
Sebastien Bourdeauducq 7e14f3ca4e compiler,gateware: atomic now stores 2018-12-02 05:06:46 +08:00
Sebastien Bourdeauducq c56c0ba41f rtio/dds: use write-only RT2WB 
This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
 2018-11-26 07:38:15 +08:00
Sebastien Bourdeauducq 09141e5bee rtio/wishbone: support write-only interface 2018-11-26 07:38:06 +08:00
Sebastien Bourdeauducq 450a035f9e suservo: move overflowing RTIO address bits into data 2018-11-26 06:54:20 +08:00
Sebastien Bourdeauducq ae8ef18f47 rtlink: sanity-check parameters 2018-11-26 01:14:02 +08:00
Sebastien Bourdeauducq 53e79f553f Merge branch 'master' into new 2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq 78d4b3a7da gateware/targets: expose variant lists 
This allows writing scripts that build all variants.
 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq 1b841805f6 Merge branch 'master' into new 2018-11-16 15:20:32 +08:00
Robert Jördens 2af6edb8f5 eem: fix reset/sync in suservo 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-13 13:00:54 +00:00
Sebastien Bourdeauducq 1f7858b80b test/dsp: fix rtio_output 2018-11-09 22:11:44 +08:00
Sebastien Bourdeauducq e509ab8553 test/dsp: use absolute import path 
Avoids "ImportError: attempted relative import with no known parent package"
when doing a simple "python -m unittest test_XXX.py".
 2018-11-09 22:10:46 +08:00
Sebastien Bourdeauducq c990b5e4f1 Merge remote-tracking branch 'origin/master' into new 2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq f74dda639f drtio: 8-bit address 2018-11-08 18:36:20 +08:00
Sebastien Bourdeauducq 8caea0e6d3 gateware,runtime: optimize RTIO kernel interface further 
* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
 2018-11-08 18:29:24 +08:00
Sebastien Bourdeauducq aadf5112b7 rtio: remove incorrect comment 2018-11-08 00:02:44 +08:00
Sebastien Bourdeauducq 3d0c3cc1cf gateware,runtime: optimize RTIO output interface 
* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
 2018-11-07 23:39:58 +08:00
Sebastien Bourdeauducq ad0254c17b Merge branch 'switching125' into new 2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq efd735a6ab Revert "drtio: monitor RTIOClockMultiplier PLL (#1155)" 
This reverts commit 469a66db61.
 2018-11-07 22:01:03 +08:00
Robert Jördens ba4bf6e59b kasli: don't pass rtio pll feedback through bufg 
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:58:55 +00:00
Robert Jördens b6e4961b0f kasli: lower RTIO clock jitter 
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:43:19 +00:00
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:06:51 +00:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock 
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:14 +01:00
Robert Jördens 4269d5ad5c tester: add urukul sync 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:52 +01:00
Robert Jördens 60d3bc63a7 ptb: back out urukul-sync 
... for backwards compatibility.

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:50 +01:00
Robert Jördens 3538444876 urukul: add sync_in to eem0-7 name 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:32 +01:00
Robert Jördens 0433e8f4fe urukul: add sync_in generator 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq bc4a8157c0 kasli: add tsinghua2 2018-11-01 18:26:37 +08:00
Sebastien Bourdeauducq 48a142ed63 use FutureWarning instead of DeprecationWarning 
DeprecationWarning is disabled by default and too easy to ignore.
 2018-10-21 12:14:51 +08:00
Sebastien Bourdeauducq 6357a50d33 kasli: update nudt variant 2018-10-15 18:04:57 +08:00
Sebastien Bourdeauducq 469a66db61 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-10-08 14:50:02 +02:00
Sebastien Bourdeauducq 86fe6b0594 kasli: add NUDT variant 2018-10-04 23:20:09 +08:00
Sebastien Bourdeauducq a89bd6b684 kasli: swap Urukul EEMs for Tester 
Updated to Urukul 1.3.
 2018-10-04 23:19:31 +08:00
Sebastien Bourdeauducq 9f96b6bcda kasli: use 125MHz DRTIO freq for testing 2018-10-04 10:41:01 +08:00
Sebastien Bourdeauducq 969a305c5a Merge branch 'master' into switching125 2018-10-04 10:08:42 +08:00
Robert Jördens d0ee2c2955 opticlock: external 100 MHz 2018-09-28 19:05:18 +02:00
Sebastien Bourdeauducq 3b3fddb5a4 kasli: add mitll2 2018-09-27 23:21:52 +08:00
Sebastien Bourdeauducq b92350b0f6 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-09-26 10:52:08 +08:00
Sebastien Bourdeauducq 212892d92f style 2018-09-26 10:13:33 +08:00
Sebastien Bourdeauducq 73f0de7c79 sayma: DRTIO master fixes 2018-09-20 11:15:45 +08:00
Sebastien Bourdeauducq 53a979e74d rtio: cleanup resets 2018-09-20 10:58:38 +08:00
Sebastien Bourdeauducq 251d90c3d5 drtio: clear read request in satellite only after reply has been fully sent 
Otherwise, chan_sel become invalid before the end of the packet, which
can cause the interconnect to invalidate i_timestamp and i_data which results
in corruption of the end of the packet.
 2018-09-20 08:53:45 +08:00
Sebastien Bourdeauducq 69d060b639 drtio: fix satellite i_status handling 2018-09-19 20:57:21 +08:00
Sebastien Bourdeauducq b86b6dcc09 drtio: add switching input test 2018-09-19 17:50:29 +08:00
Sebastien Bourdeauducq 08be176369 drtio: fix satellite i_status handling 2018-09-19 17:50:18 +08:00
Sebastien Bourdeauducq 3d965910f7 Revert "drtio: implement per-destination underflow margins" 
This reverts commit 142c952e3d.
 2018-09-19 17:05:48 +08:00
Sebastien Bourdeauducq 142c952e3d drtio: implement per-destination underflow margins 2018-09-19 17:03:15 +08:00
Sebastien Bourdeauducq 970d1bf147 drtio: add switching unittest 2018-09-18 15:27:52 +08:00
Sebastien Bourdeauducq eda15a596c drtio: add buffering to repeater 2018-09-18 15:27:25 +08:00
Sebastien Bourdeauducq 2b44786f73 drtio: add repeater input support 2018-09-17 23:45:27 +08:00
Sebastien Bourdeauducq d38755feff drtio: implement destination state checks on operations 2018-09-15 15:55:45 +08:00
Sebastien Bourdeauducq cd61ee858c kasli: fix satellite TSC instantiation 2018-09-15 14:06:54 +08:00
Sebastien Bourdeauducq 1ef39a98a7 drtio: implement per-destination buffer space 2018-09-13 16:16:32 +08:00
Sebastien Bourdeauducq 0befec7d26 drtio: improve repeater error reports 2018-09-12 20:54:01 +08:00
Sebastien Bourdeauducq 420e1cb1d0 cri: fix firmware routing table access 2018-09-12 18:08:16 +08:00
Sebastien Bourdeauducq 5bcd40ff59 cri: fix routing table depth 2018-09-12 17:30:55 +08:00
Sebastien Bourdeauducq edf403b837 drtio: improve error reporting 2018-09-12 15:44:34 +08:00
Sebastien Bourdeauducq 95432a4ac1 drtio: remove old debugging features 2018-09-12 13:01:27 +08:00
Sebastien Bourdeauducq 41972d6773 drtio: rt_packet_satellite CRI fixes 2018-09-11 22:19:55 +08:00
Sebastien Bourdeauducq 051bafbfd9 drtio: ensure 2 cycles between frames on the link 
This gives time for setting chan_sel before cmd on CRI.
 2018-09-11 22:18:42 +08:00
Sebastien Bourdeauducq 251b9a2b0d drtio: do not lock up master when satellite repeatedly fails to answer buffer space reqs 2018-09-11 22:17:57 +08:00
Sebastien Bourdeauducq 7ec45efdcf kasli: add missing cri_con to Satellite 2018-09-10 20:16:09 +08:00
Sebastien Bourdeauducq 7ae44f3417 firmware: add routing table (WIP) 2018-09-09 21:49:28 +08:00
Sebastien Bourdeauducq 496d1b08fd kasli: enable routing in Master 2018-09-09 21:48:12 +08:00
Sebastien Bourdeauducq ec302747e0 kasli: add DRTIO repeaters 2018-09-09 16:27:39 +08:00
Sebastien Bourdeauducq d5577ec0d0 cri: add routing table support 2018-09-09 16:26:48 +08:00
Sebastien Bourdeauducq df61b85988 drtio: fix imports 2018-09-09 14:11:32 +08:00
Robert Jördens 312256a18d grabber: fix frame size off-by-1 2018-09-07 16:55:43 +02:00
Sebastien Bourdeauducq ec62eb9373 drtio: minor cleanup 2018-09-07 17:51:38 +08:00
Robert Jördens 4d73fb5bc9 grabber: only advance when DVAL 2018-09-06 11:01:08 +02:00
Sebastien Bourdeauducq 87e0384e97 drtio: separate aux controller 
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
 2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq 92be9324df add missing files 2018-09-05 16:09:02 +08:00
Sebastien Bourdeauducq 2884d595b3 drtio: add rt_controller_repeater 2018-09-05 16:08:40 +08:00
Sebastien Bourdeauducq 839f748a1d drtio: add external TSC to repeater 2018-09-05 15:55:20 +08:00
Sebastien Bourdeauducq 5f20d79408 drtio: add timeout on satellite internal CRI buffer space request 2018-09-05 14:12:11 +08:00
Sebastien Bourdeauducq 1450e17a73 sayma: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:10:41 +08:00
Sebastien Bourdeauducq 19ae9ac1b1 kc705: adapt to TSC changes 2018-09-05 12:07:28 +08:00
Sebastien Bourdeauducq 3d531cc923 kasli: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:06:47 +08:00
Sebastien Bourdeauducq 4e4398afa6 analyzer: adapt to TSC changes 2018-09-05 12:06:20 +08:00
Robert Jördens 47eb37e212 VLBAI{Master,Slave}: align rtio channels with PTB 2018-09-04 10:39:45 +00:00
Sebastien Bourdeauducq 778f1de121 drtio: add TSC sync and missed command detection to rt_packet_repeater 2018-09-03 18:26:13 +08:00
hartytp c55460f59f suservo: fix doc typo 2018-09-03 11:48:40 +02:00
Sebastien Bourdeauducq 00fabee1ca drtio: fix rt_packet_repeater timeout 2018-09-03 09:57:15 +08:00
Sebastien Bourdeauducq f3fe818049 rtio: refactor TSC to allow sharing between cores 2018-09-03 09:48:12 +08:00
Sebastien Bourdeauducq 0fe2a6801e drtio: forward destination with channel 2018-09-02 15:50:23 +08:00
Sebastien Bourdeauducq 6768dbab6c drtio: add buffer space support to rt_packet_repeater 2018-09-02 14:38:37 +08:00
Sebastien Bourdeauducq 88b7529d09 drtio: share CDC 2018-09-02 14:37:29 +08:00
Sebastien Bourdeauducq 078c862618 drtio: add repeater (WIP, write only) 2018-09-01 21:07:55 +08:00
Sebastien Bourdeauducq 6057cb797c drtio: reorganize tests 2018-08-31 16:28:33 +08:00
Sebastien Bourdeauducq 4f963e1e11 drtio: minor cleanup 2018-08-30 15:15:32 +08:00
Sebastien Bourdeauducq ce6e390d5f drtio: expose internal satellite CRI 2018-08-30 12:41:09 +08:00
Robert Jördens e7dba34475 kasli/tester: fill all 12 EEM 2018-08-29 18:09:09 +00:00
Robert Jördens fbf05db5ab kasli: add VLBAI Master and Satellite 2018-08-29 17:53:48 +00:00
Robert Jördens 9584c30a1f kasli: DRTIO Base: flexible rtio_clk_freq 2018-08-29 17:53:48 +00:00
Robert Jördens eb9e9634df siphaser: support 125 MHz rtio clk 
keep the phase shift increment/decrement at 1/(56*8) rtio_clk
cycles
 2018-08-29 17:53:48 +00:00
Sebastien Bourdeauducq aa64e6c1c6 cri: add buffer space request protocol 2018-08-29 15:16:43 +08:00
Sebastien Bourdeauducq 9b6ea47b7a kasli: use SFP LEDs to show DRTIO link status. Closes #1073 2018-08-19 13:04:41 +08:00
Sebastien Bourdeauducq 167e97efd2 sayma: support external RTM clocking 2018-08-17 22:57:54 +08:00
Sebastien Bourdeauducq 041dc0f64a jesd204: update core to v0.10 
Closes #727
Closes #1127
 2018-08-17 22:50:07 +08:00
Sebastien Bourdeauducq 49f7a1610f sayma: use GTP_CLK1 only for all variants (#1080) 2018-08-07 20:53:14 +08:00
Sebastien Bourdeauducq e2a49ce368 drtio: support external IBUFDS_GTE3 2018-08-07 20:52:45 +08:00
Sebastien Bourdeauducq 9ce6233926 kasli: fix SYSU TTL directions 2018-08-07 19:29:28 +08:00
Sebastien Bourdeauducq 65f198bdee kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example 2018-08-06 16:53:13 +08:00
Sebastien Bourdeauducq b023865b42 sayma: instantiate dummy IBUFDS_GTE3 on unused but driven Si5324 clock pins 
Solve same problem as e83ee3a0 but channels cannot be independently disabled.
 2018-08-05 23:02:41 +08:00
Sebastien Bourdeauducq e83ee3a07a hmc7043: disable GTP_CLK1 when not in use 
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
 2018-08-03 10:03:52 +08:00
Sebastien Bourdeauducq b38c685857 grabber: fix pix.stb 2018-07-24 11:32:32 +08:00
Sebastien Bourdeauducq 60a7e0e40d grabber: use usual order of ROI coordinates in cfg addresses 2018-07-24 10:55:13 +08:00
Sebastien Bourdeauducq 7b75026391 grabber: add MultiReg to transfer ROI boundaries 2018-07-21 13:40:12 +08:00
Sebastien Bourdeauducq 4a4d0f8e51 grabber: fix missing variable rename 2018-07-21 13:39:46 +08:00
Sebastien Bourdeauducq 3638a966e1 kasli: add false path between RTIO and CL clocks 2018-07-21 13:26:13 +08:00
Sebastien Bourdeauducq 031de58d21 grabber: complete RTIO PHY, untested 2018-07-21 13:25:47 +08:00
Sebastien Bourdeauducq e3ba4b9516 grabber: minor ROI engine cleanup, export count_len, cap count width to 31 2018-07-21 13:25:13 +08:00
Sebastien Bourdeauducq 25170a53e5 sayma: add back Urukul and Zotino 2018-07-18 10:27:54 +08:00
Sebastien Bourdeauducq 7fe76426fe fmcdio_vhdci_eem: commit missing part of previous commit 2018-07-17 20:30:13 +08:00
Sebastien Bourdeauducq 4fdc20bb11 sayma: disable Urukul and Zotino for now 
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
 2018-07-17 20:08:21 +08:00
Sebastien Bourdeauducq 8335085fd6 fmcdio_vhdci_eem: fix cc pins 2018-07-17 19:50:34 +08:00
Sebastien Bourdeauducq 8f7c0c1646 fmcdio_vhdci_eem: fix iostandard 2018-07-17 19:40:34 +08:00
Sebastien Bourdeauducq d724bd980c sayma: add EEMs to Master 2018-07-17 18:58:23 +08:00
Sebastien Bourdeauducq a0f2d8c2ea gateware: add FMCDIO/EEM adapter definitions 2018-07-17 18:58:16 +08:00
Sebastien Bourdeauducq 3645a6424e sayma: fix Master build 2018-07-17 18:56:33 +08:00
Sebastien Bourdeauducq 9b016dcd6d eem: support specifying I/O standard 
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
 2018-07-17 18:55:17 +08:00
Sebastien Bourdeauducq 3168b193e6 kc705: remove Zotino and Urukul 
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
 2018-07-17 17:48:57 +08:00
Sebastien Bourdeauducq b2695d03ed sayma: remove with_sawg from Master variant 2018-07-15 17:38:29 +08:00
Sebastien Bourdeauducq b27fa8964b add variant in identifier string 
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
 2018-07-15 17:21:17 +08:00
Sebastien Bourdeauducq b6c70b3cb0 eem: add Zotino monitoring. Closes #1095 2018-07-15 15:35:04 +08:00
Sebastien Bourdeauducq 8bcba82b65 grabber: reset *_good signals on end of frame 
This reduces the amount of time the ROI engine produces invalid output after
being reconfigured.
 2018-07-15 15:34:00 +08:00
Sebastien Bourdeauducq 82def6b535 grabber: add frequency counter 
Cameras are a bit obscure about what they output, this can help with troubleshooting.
 2018-07-12 17:05:18 +08:00
Sebastien Bourdeauducq 88fb9ce4d6 sayma_rtm: add hmc7043_gpo monitoring 2018-07-11 19:04:29 +08:00
Sebastien Bourdeauducq 29e5c95afa sayma_rtm: minor cleanup 2018-07-11 19:02:59 +08:00
Sebastien Bourdeauducq 7f05e0c121 sayma_rtm: remove UART loopback 
RTM power supply issues are fixed now, plus this will get in the way of satman support.
 2018-07-11 19:00:18 +08:00
Sebastien Bourdeauducq f8ceea20d0 grabber: add new ROI engine (untested) 2018-07-10 17:06:17 +08:00
Sebastien Bourdeauducq d82beee540 grabber: make parser EOP a pulse 2018-07-10 17:04:07 +08:00
Sebastien Bourdeauducq 701c93d46c grabber: add false path constraints 2018-07-10 14:28:23 +08:00
Sebastien Bourdeauducq 6a77032fa5 grabber: use BUFR/BUFIO 
Less jitter and frees up BUFGs.
 2018-07-10 13:30:38 +08:00
Sebastien Bourdeauducq 208dc7c218 grabber: prevent glitches in last_x/last_y cdc 2018-07-10 12:56:37 +08:00
Sebastien Bourdeauducq c4e3c66265 grabber: add clock constraint 2018-07-10 12:37:32 +08:00
Sebastien Bourdeauducq 4f56710e4b grabber: add parser, report detected frame size in core device log 2018-07-10 02:06:37 +08:00
Sebastien Bourdeauducq 509562ddbf kasli: add WIPM target 2018-07-06 15:41:28 +08:00
Sebastien Bourdeauducq 540bdae99c grabber: enable DIFF_TERM on inputs 2018-07-01 09:28:51 +08:00
Sebastien Bourdeauducq 729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver 
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
 2018-06-28 11:23:40 +08:00
Sebastien Bourdeauducq a65721d649 sayma: put RTM clock tree into the siphaser loop 
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
 2018-06-27 21:46:55 +08:00
Sebastien Bourdeauducq c750de2955 sayma: add many-port pure DRTIO master 2018-06-25 18:21:22 +08:00
Sebastien Bourdeauducq 68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets 
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
 2018-06-23 10:44:38 +08:00
Sebastien Bourdeauducq f87da95e57 jesd204: use jesd clock domain for sysref sampler 
RTIO domain is still in reset during calibration.
 2018-06-22 17:13:01 +08:00
Sebastien Bourdeauducq 76fc63bbf7 jesd204: use separate controls for reset and input buffer disable 2018-06-22 11:38:18 +08:00
Sebastien Bourdeauducq d9955fee76 jesd204: make sure IOB FF is used to sample SYSREF at FPGA 2018-06-22 11:00:56 +08:00
Sebastien Bourdeauducq 60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz 2018-06-22 10:10:09 +08:00
Sebastien Bourdeauducq e6d1726754 sayma: add RTIO log to DRTIO master 2018-06-22 00:05:22 +08:00
Sebastien Bourdeauducq 83428961ad sayma: add SAWG and JESD to DRTIO master 2018-06-22 00:04:22 +08:00
Sebastien Bourdeauducq c1db02a351 drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin 
Precaution against HMC7043 noise issues.
 2018-06-21 22:56:07 +08:00
Sebastien Bourdeauducq 8b3c12e6eb sayma: clock DRTIO master transceiver from HMC7043 2018-06-21 22:34:44 +08:00
Sebastien Bourdeauducq de7d64d482 sayma: clock JESD204 from GTP CLK2 
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
 2018-06-21 22:33:53 +08:00
Sebastien Bourdeauducq b28ff587c5 sayma: add sysref sampler to DRTIO master 2018-06-21 22:28:34 +08:00
Sebastien Bourdeauducq e29536351d drtio: resync SYSREF when TSC is loaded 2018-06-21 17:00:32 +08:00
Sebastien Bourdeauducq 45e8263208 hmc7043: do not configure phases during initial init 
They are determined later on.
 2018-06-21 15:54:42 +08:00
Sebastien Bourdeauducq 28fb0fd754 sayma: add SYSREF sampler gateware 2018-06-20 17:48:35 +08:00
Sebastien Bourdeauducq 9142a5ab8a rtio: expose coarse timestamp in RTIO and DRTIO satellite cores 2018-06-20 17:39:54 +08:00
Sebastien Bourdeauducq 75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq 433273dd95 sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite 2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq 6403a0d5d1 sayma_amc: update without-sawg description 2018-06-19 13:52:05 +08:00
Sebastien Bourdeauducq d29b3dd588 hmc830: compile-time configurable reference frequency 2018-06-19 13:47:32 +08:00
Sebastien Bourdeauducq 6f3ed81626 targets/sayma_rtm: fix description 2018-06-18 17:46:53 +08:00
Robert Jördens 32484a62de sayma_amc: remove unused imports 2018-06-17 13:09:44 +02:00
Robert Jördens 53ab255c00 sayma_amc: enable slave fpga loading (#813) 2018-06-16 12:47:26 +02:00
Robert Jördens 1029ac870b sayma_rtm: don't drive txen pins 
pins disabled by config
necessary for using that pin as DIN (#813)
 2018-06-13 16:11:30 +00:00
Sebastien Bourdeauducq 68d16fc292 serwb: support single-ended signals 
Low-speed PHY only.
 2018-06-13 21:28:21 +08:00
Robert Jördens a9a25f2605 sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early 2018-06-12 20:00:12 +02:00
Robert Jördens a143e238a8 savel_fpga: get rid of unneeded config 2018-06-12 10:24:04 +02:00
Robert Jördens 0b086225a9 sawg: don't use Cat() for signed signals 
c.f. #1039 #1040 #1022 #1058 #1044
 2018-06-09 07:33:47 +00:00
Robert Jördens 5b73dd8604 sawg: accurate unittest rtio freq 2018-06-08 17:22:13 +02:00
Robert Jördens e5f6750171 sawg: cleanup double assign 2018-06-08 14:31:55 +00:00
Florent Kermarrec 53e9e475d0 serwb: transmit zeroes when nothing to transmit (for prbs), improve rx idle detection 2018-06-08 16:10:31 +02:00
Florent Kermarrec 7296a76f18 serwb: move common datapath code to datapath.py, simplify flow control 2018-06-08 12:37:08 +02:00
Florent Kermarrec 89797d08ed serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds) 2018-06-07 15:13:56 +02:00
Robert Jördens b4c2b148d1 sawg: don't use Mux for signed signals 
migen#75
 2018-06-06 15:51:14 +00:00
Florent Kermarrec 009db5eda9 serwb: revert 1gbps linerate 2018-06-06 16:20:20 +02:00
Sebastien Bourdeauducq cae92f9b44 kasli: add Tsinghua variant 2018-06-06 19:03:45 +08:00
Robert Jördens e21b7965b9 sayma_amc: change test patterns for 'without-sawg' 2018-06-06 08:02:52 +00:00
Sebastien Bourdeauducq af88c4c93e clean up hmc7043 reset 2018-06-05 20:41:48 +08:00
Thomas Harty ac5c4913ec Sayma RTM: hold hmc7043 in reset/mute state during init. 2018-06-05 19:22:04 +08:00
Chris Ballance 07d4145a35 correct documented siphaser VCO frequency [NFC] 2018-06-04 20:53:43 +08:00
Robert Jördens bb87976d4f suservo: docstring fixes, revert parametrization of r_rtt 2018-06-04 07:27:17 +00:00
Robert Jördens 07a1425e51
SUservo EEM docs 
add documentation to eem.SUServo. Change parameterization of t_rtt to include delays on Sampler, as this seems simpler and more robust to changing RTIO frequencies in the future.

c.f. #1046
 2018-06-04 08:51:28 +02:00
Robert Jördens f50aef1a22 suservo: extract boilerplate 
closes #1041
 2018-06-01 15:37:07 +00:00
Robert Jördens 9b5a46dffd suservo: fix restart counter assertion 
c.f. #788
 2018-05-31 15:56:11 +00:00
Paweł 44c7a028cb Added second argument to DIO.add_STD in master and satellite variant of kasli (now builds properly) 2018-05-30 22:49:40 +08:00
Sebastien Bourdeauducq ad099edf63 kasli: integrate grabber 2018-05-28 22:43:40 +08:00
Sebastien Bourdeauducq 563e434e15 eem: finalize grabber support 2018-05-28 22:43:06 +08:00
Sebastien Bourdeauducq 2612fd1e72 rtio: add grabber deserializer and WIP PHY encapsulation 2018-05-28 22:42:27 +08:00
Florent Kermarrec e21f14c0b3 serwb/phy: typo (KUSSerdes --> KUSerdes) 2018-05-28 10:41:11 +02:00
Robert Jördens b20a8c86b0 kasli: don't bother with grabber ttls for now 
not used on target cameras
 2018-05-28 07:31:00 +02:00
Sebastien Bourdeauducq 80c69da17e eem: add Grabber IOs and CC 2018-05-28 11:16:23 +08:00
Sebastien Bourdeauducq bb248970df style 2018-05-28 10:40:05 +08:00
Robert Jördens b09d07905c kasli: add LUH/PTB/HUB variants 
and refactor/simplify variant selection
 2018-05-27 18:33:27 +00:00
Florent Kermarrec bca2969957 sayma_rtm: add RTMScratch module to test remote Wishbone accesses 2018-05-24 16:53:10 +02:00
Sebastien Bourdeauducq 19efd8b13e kasli: refactor EEM code 2018-05-24 18:41:54 +08:00
Sebastien Bourdeauducq 4e5fe672e7 kasli: add tester target 2018-05-21 17:43:39 +08:00
Sebastien Bourdeauducq 72aef5799e kasli/ustc: use TTLOut 2018-05-18 22:55:28 +08:00
Sebastien Bourdeauducq b10d3ee4b4 make RTIO clock switch optional and simplify 
Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
 2018-05-18 17:41:34 +08:00
Sebastien Bourdeauducq 8a988d0feb kasli: remove leftover debug print 2018-05-18 17:25:23 +08:00
Sebastien Bourdeauducq 37bd0c2566 kasli: add USTC target 2018-05-18 16:15:07 +08:00
Florent Kermarrec f77bcbebb5 serwb/test_serwb_core: fix 2018-05-16 08:34:53 +02:00
Florent Kermarrec 77fc5c599f serwb/test: update 2018-05-15 23:52:58 +02:00
Florent Kermarrec 3873d09692 serwb: rewrite high-speed phys by splitting clocking/tx/rx, scrambling is now always enabled. 2018-05-15 23:52:41 +02:00
Florent Kermarrec f8a9dd930b serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled. 2018-05-15 23:51:14 +02:00
Florent Kermarrec 2c627cd061 serwb/scrambler: simplify and set scrambler input data to 0 when sink.stb == 0 2018-05-15 23:49:17 +02:00
Florent Kermarrec c18a73d45f sayma_amc/rtm: use new serwb low-speed phy 2018-05-15 16:40:50 +02:00
Florent Kermarrec 913d1e8e12 serwb: add generic low-speed phy (125Mhz linerate, same phy for ultrascale/7-series) 2018-05-15 16:39:39 +02:00
Florent Kermarrec 520aade8fe serwb/scrambler: cleanup/fix potential bug 2018-05-15 16:30:52 +02:00
Robert Jördens 504d37b66b suservo: add SI units functions and document 
m-labs/artiq#788
 2018-05-14 12:26:49 +00:00
Robert Jördens d71e4e60a9 suservo: use addition for offset 2018-05-14 12:26:49 +00:00
Robert Jördens 27f975e7bb kasli: eem DifferentialInputs need DIFF_TERM 
cleanup some formatting on the way
 2018-05-14 12:26:49 +00:00
Robert Jördens 2a47b934ea suservo: remove adc return clock gating 2018-05-14 12:26:49 +00:00
Robert Jördens 74c0b4452b suservo: clkout and sdo[b-d] are inverted 2018-05-14 12:26:49 +00:00
Robert Jördens 04240cdc08 suservo: sampler channels are reversed 2018-05-14 12:25:09 +00:00
Sebastien Bourdeauducq 3027951dd8 integrate new AD9914 driver 
moninj, analyzer, docs, examples, tests.
 2018-05-13 23:29:35 +08:00
whitequark ee4c475cf3 gateware: fix Sayma satellite build. 
RTIO clock multiplier was removed from Sayma in 32f22f4c.
 2018-05-13 13:10:39 +00:00
Sebastien Bourdeauducq 8c1390e557 kasli: use 62.5MHz clock for siphaser reference (#999) 2018-05-12 22:58:03 +08:00
Sebastien Bourdeauducq 2426fea3f2 siphaser: support external reference for the freerunning 150MHz 2018-05-12 22:57:11 +08:00
Sebastien Bourdeauducq 6796413a53 serwb: remove unnecessary shebang line 2018-05-12 22:49:44 +08:00
Florent Kermarrec f5208ff2f3 serwb/core: reduce buffering, use buffered=True 2018-05-12 12:03:58 +02:00
Florent Kermarrec fdc953e569 serwb/etherbone: recuce buffering 2018-05-12 12:03:11 +02:00
Florent Kermarrec 6e67e6d0b1 serwb: revert some changes (was breaking simulation) 2018-05-12 11:59:46 +02:00
Florent Kermarrec 0a6d4ccd85 serwb/phy: improve/cleanup init 2018-05-12 01:35:34 +02:00
Florent Kermarrec b6ab59fb80 serwb/phy: increase timeout 2018-05-12 01:32:55 +02:00
Florent Kermarrec e09dbc89bc serwb: remove idelaye3 en_vtc (was not done correctly, we'll add direct software control) 2018-05-12 01:32:16 +02:00
Florent Kermarrec cd4477864a serwb: fix case when rtm fpga is not loaded, lvds input can be 0 or 1 2018-05-11 23:31:25 +02:00
Sebastien Bourdeauducq 2e3bf8602f serwb: reduce buffering. Closes #997 2018-05-11 14:13:41 +08:00
Sebastien Bourdeauducq 6b811c1a8b sayma: fix runtime/rtm gateware address conflict 2018-05-09 19:47:29 +08:00
Robert Jördens f055bf88f6 suservo: add clip flags (#992) 2018-05-09 07:16:15 +00:00
Florent Kermarrec 60fd362d57 serwb: fix rx_comma detection 2018-05-07 23:54:35 +02:00
Robert Jördens 7d4a103a43 opticlock, suservo: set default kasli hw_rev 2018-05-07 09:07:18 +02:00
whitequark b1d349cc1b firmware: implement a sampling profiler. 
Does not yet support constructing call graphs.
 2018-05-05 00:44:40 +00:00
Sebastien Bourdeauducq 5f0cfadb30 rtio/sed: add unittest for sequence number rollover 2018-05-02 12:04:30 +08:00
Sebastien Bourdeauducq 4120105e3a rtio/sed: fix output network cmp_wrap 2018-05-02 12:04:03 +08:00
Sebastien Bourdeauducq bce8fa3ec5 rtio/sed: add replace unittest at the top level (#978) 2018-05-02 10:58:18 +08:00
Sebastien Bourdeauducq 83fb431cd0 rtio/sed: pass sequence numbers through the FIFOs. Closes #978 2018-05-02 10:57:57 +08:00
Florent Kermarrec 05955bfd79 sayma_rtm: use bufio for sys4x (needed since we are using a -1 speedgrade) 2018-05-01 22:16:35 +02:00
Florent Kermarrec 84e1f05559 sayma_rtm: make cd_sys4x clock domain reset_less 2018-05-01 16:11:26 +02:00
Florent Kermarrec 64c8eee28d serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded) 2018-04-30 23:59:56 +02:00
Robert Jördens 5a683ddd1f Revert "kasli: force hw_rev for the different targets" 
This reverts commit 17d7d7856a.

Would require filtering it in misoc or better
removing the argparse option.
 2018-04-28 23:24:41 +02:00
Robert Jördens 17d7d7856a kasli: force hw_rev for the different targets 2018-04-28 21:30:29 +02:00
Robert Jördens 5d3c76fd50 sayma_rtm: use bitstream opts in migen 2018-04-27 15:43:32 +00:00
Robert Jördens 5f00326c65 suservo: coeff mem write port READ_FIRST 2018-04-27 15:43:32 +00:00
Robert Jördens 307cd07b9d suservo: lots of gateware/ runtime changes 
tested/validated:

* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback

individual changes below:

suservo: correct rtio readback

suservo: example, device_db [wip]

suservo: change rtio channel layout

suservo: mem ports in rio domain

suservo: sck clocked from rio_phy

suservo: cleanup, straighten out timing

suservo: dds cs polarity

suservo: simplify pipeline

suservo: drop unused eem names

suservo: decouple adc SR from IIR

suservo: expand coredevice layer

suservo: start the correct stage

suservo: actually load ctrl

suservo: refactor/tweak adc timing

suservo: implement cpld and dds init
 2018-04-27 13:50:26 +02:00
Florent Kermarrec 8212e46f5e sayma_amc: filter jesd refclk/sysref with jreset (hmc7043 can generate noise when unconfigured see sinara issue #541) 2018-04-27 13:04:37 +02:00
Robert Jördens f9b2c32739 suservo: add pgia spi channel 2018-04-25 17:14:25 +00:00
Robert Jördens c83305065a suservo: add servo/config/status register 2018-04-25 15:59:06 +00:00
Robert Jördens 105068ad90 suservo: fix restart timing 2018-04-25 15:19:49 +00:00
Robert Jördens c304b6207a suservo: drop adc idelays 2018-04-25 14:59:50 +00:00
Robert Jördens b44d6517d1 suservo: use 125 MHz SDR ADC 
* easier timing
* natural sampling on rising edge
* timing, signal robustness
* adjust the servo iteration timing
 2018-04-25 14:32:23 +00:00
Robert Jördens 37c186a0fc suservo: refactor, constrain 
* remove DiffMixin, move pad layout handling to pads
* add input delay constraints, IDELAYs
 2018-04-25 13:44:52 +00:00
Robert Jördens d0258b9b2d suservo: set input delays 2018-04-24 15:30:25 +00:00
Robert Jördens fe75064c1e suservo: cleanup rtio interface 2018-04-24 13:08:40 +00:00
Robert Jördens 3942c2d274 suservo: fix clkout cd drive 2018-04-24 10:18:32 +00:00
Robert Jördens f74998a5e0 suservo: move arch logic to top, fix tests 2018-04-23 21:11:26 +00:00
Robert Jördens 4903eb074c suservo: use BUFIO/BUFH for ADC 2018-04-23 18:30:19 +00:00
Robert Jördens e36deab0a8 suservo/adc: try to help vivado extract srls 2018-04-23 18:30:19 +00:00
Robert Jördens 929ed4471b kasli/SUServo: use suservo, implement urukul_qspi 
m-labs/artiq#788
 2018-04-23 18:30:18 +00:00
Robert Jördens 4c1e356f67 suservo: add pads rewiring layer for eems 2018-04-23 18:30:18 +00:00
Robert Jördens 99dd9c7a2a suservo: fix rtio interface width 2018-04-23 18:30:18 +00:00
Robert Jördens d5eea962ec suservo: fix cnv_b diff 2018-04-23 18:30:12 +00:00
Robert Jördens c8fd63754a suservo: add unittests 
m-labs/artiq#788
 2018-04-23 18:25:59 +00:00
Robert Jördens 934c41b90a gateware: add suservo 
from
fe4b60b902

m-labs/artiq#788
 2018-04-23 18:24:59 +00:00
Florent Kermarrec 439d2bf2bc sayma/serwb: adapt, full reset of rtm on link reset 2018-04-17 19:24:03 +02:00
Florent Kermarrec 8edf4541d6 serwb: adapt test 2018-04-17 19:21:53 +02:00
Florent Kermarrec 20ccc9d82f serwb/core/phy: move scrambler in phy, add link test, revert delay min/max checks 2018-04-17 19:21:21 +02:00
Florent Kermarrec ebfac36223 serwb/scrambler: dynamic enable/disable 2018-04-17 19:20:06 +02:00
Florent Kermarrec 816a6f2ec7 serwb/phys: remove phy_width (revert linerate to 1Gbps) 2018-04-17 19:19:18 +02:00
Sebastien Bourdeauducq eac447278f kasli: add MITLL variant 2018-04-17 19:00:11 +08:00
Sebastien Bourdeauducq 756e120c27 kasli/sysu: add comments 2018-04-17 18:46:55 +08:00
Florent Kermarrec 1acd7ea1db sayma/serwb: re-enable scrambling 2018-04-17 00:49:36 +02:00
Florent Kermarrec ca01c8f1cb sayma: reduce serwb linerate to 500Mbps 2018-04-16 23:19:15 +02:00
Florent Kermarrec 825a2158ba serwb: add phy_width parameter to allow reducing linerate to 500Mbps or 250Mbps 2018-04-16 23:19:14 +02:00
Florent Kermarrec bb90fb7d59 sayma/serwb: remove scrambling (does not seems to work on sayma for now...) 2018-04-07 15:57:57 +02:00
Florent Kermarrec 6aa8e2c433 serwb/test: replace valid/ready with stb/ack 2018-04-07 15:55:57 +02:00
Florent Kermarrec 73dbc0b6b6 serwb/test: adapt to new version 2018-04-07 15:09:29 +02:00
Florent Kermarrec e15f8aa903 sayma/serwb: enable scrambling 2018-04-07 14:52:37 +02:00
Florent Kermarrec 9d0e8c27ff serwb/scrambler: add flow control 2018-04-07 14:51:17 +02:00
Florent Kermarrec 2f8bd022f7 sayma_rtm: remove sys0p2x clock 2018-04-07 03:10:34 +02:00
Florent Kermarrec 1fd96eb0fd serwb: replace valid/ready with stb/ack 2018-04-07 03:06:19 +02:00
Florent Kermarrec c8a08375f8 serwb: replace valid/ready with stb/ack 2018-04-07 03:03:44 +02:00
Florent Kermarrec 73b727cade serwb: new version using only sys/sys4x clocks domains, scrambling deactivated. 2018-04-07 02:59:14 +02:00
Florent Kermarrec dd21c07b85 targets/sayma_rtm: fix serwb 2 ... 2018-04-03 18:59:05 +02:00
Florent Kermarrec 7488703f23 targets/sayma_rtm: fix serwb 2018-04-03 18:57:00 +02:00
Florent Kermarrec aef0153a8f targets/sayma: adapt to new serwb clocking 2018-04-03 18:53:39 +02:00
Florent Kermarrec 3248caa184 gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks 2018-04-03 18:48:08 +02:00
Sebastien Bourdeauducq f0771765c1 rtio: move CRI write comment to more appropriate location 2018-03-29 23:55:00 +08:00