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drtio: add switching unittest
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165
artiq/gateware/test/drtio/test_switching.py
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165
artiq/gateware/test/drtio/test_switching.py
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import unittest
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from types import SimpleNamespace
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import random
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from migen import *
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from artiq.gateware.drtio import *
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from artiq.gateware.drtio import rt_serializer, rt_packet_repeater
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from artiq.gateware import rtio
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from artiq.gateware.rtio import cri
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from artiq.coredevice.exceptions import *
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from artiq.gateware.test.drtio.packet_interface import PacketInterface
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class DummyTransceiverPair:
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def __init__(self, nwords):
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a2b_k = [Signal() for _ in range(nwords)]
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a2b_d = [Signal(8) for _ in range(nwords)]
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b2a_k = [Signal() for _ in range(nwords)]
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b2a_d = [Signal(8) for _ in range(nwords)]
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self.alice = SimpleNamespace(
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encoder=SimpleNamespace(k=a2b_k, d=a2b_d),
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decoders=[SimpleNamespace(k=k, d=d) for k, d in zip(b2a_k, b2a_d)],
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rx_ready=1
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)
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self.bob = SimpleNamespace(
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encoder=SimpleNamespace(k=b2a_k, d=b2a_d),
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decoders=[SimpleNamespace(k=k, d=d) for k, d in zip(a2b_k, a2b_d)],
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rx_ready=1
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)
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class DummyRXSynchronizer:
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def resync(self, signal):
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return signal
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class DUT(Module):
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def __init__(self, nwords):
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.tsc_master = rtio.TSC("async")
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self.submodules.master = DRTIOMaster(self.tsc_master,
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self.transceivers.alice)
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self.master.rt_controller.csrs.link_up.storage.reset = 1
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rx_synchronizer = DummyRXSynchronizer()
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self.submodules.tsc_satellite = rtio.TSC("sync")
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self.submodules.satellite = DRTIOSatellite(
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self.tsc_satellite, self.transceivers.bob, rx_synchronizer)
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self.satellite.reset.storage.reset = 0
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self.satellite.reset.storage_full.reset = 0
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self.satellite.reset_phy.storage.reset = 0
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self.satellite.reset_phy.storage_full.reset = 0
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self.pt = PacketInterface("s2m", nwords*8)
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self.pr = PacketInterface("m2s", nwords*8)
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rep_if = SimpleNamespace(
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rx_rt_frame=self.pt.frame, rx_rt_data=self.pt.data,
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tx_rt_frame=self.pr.frame, tx_rt_data=self.pr.data)
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self.submodules.repeater = rt_packet_repeater.RTPacketRepeater(
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self.tsc_satellite, rep_if)
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self.comb += self.satellite.cri.connect(self.repeater.cri)
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class Testbench:
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def __init__(self):
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self.dut = DUT(2)
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self.now = 0
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def init(self):
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yield from self.dut.master.rt_controller.csrs.underflow_margin.write(100)
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while not (yield from self.dut.master.link_layer.rx_up.read()):
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yield
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yield from self.get_buffer_space()
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def get_buffer_space(self):
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csrs = self.dut.master.rt_controller.csrs
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yield from csrs.o_get_buffer_space.write(1)
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yield
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while (yield from csrs.o_wait.read()):
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yield
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r = (yield from csrs.o_dbg_buffer_space.read())
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return r
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def delay(self, dt):
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self.now += dt
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def write(self, channel, data):
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mcri = self.dut.master.cri
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yield mcri.chan_sel.eq(channel)
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yield mcri.timestamp.eq(self.now)
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yield mcri.o_data.eq(data)
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yield
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yield mcri.cmd.eq(cri.commands["write"])
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yield
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yield mcri.cmd.eq(cri.commands["nop"])
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yield
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status = yield mcri.o_status
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while status & 0x1:
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yield
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status = yield mcri.o_status
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if status & 0x2:
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return "underflow"
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if status & 0x4:
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return "destination unreachable"
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class TestSwitching(unittest.TestCase):
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5,
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"rio": 5, "rio_phy": 5,
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"sys_with_rst": 8, "rtio_with_rst": 5}
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def test_switching(self):
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tb = Testbench()
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def test():
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yield from tb.init()
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tb.delay(200)
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yield from tb.write(1, 20)
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for _ in range(40):
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yield
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current_request = None
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def get_request():
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nonlocal current_request
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while current_request is None:
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yield
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r = current_request
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current_request = None
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return r
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def expect_buffer_space_request(destination, space):
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packet_type, field_dict, trailer = yield from get_request()
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self.assertEqual(packet_type, "buffer_space_request")
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self.assertEqual(trailer, [])
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self.assertEqual(field_dict["destination"], destination)
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yield from tb.dut.pt.send("buffer_space_reply", space=space)
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def expect_write(timestamp, channel, data):
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packet_type, field_dict, trailer = yield from get_request()
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self.assertEqual(packet_type, "write")
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self.assertEqual(trailer, [])
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self.assertEqual(field_dict["timestamp"], timestamp)
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self.assertEqual(field_dict["chan_sel"], channel)
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self.assertEqual(field_dict["short_data"], data)
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@passive
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def send_replies():
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yield from expect_buffer_space_request(0, 1)
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yield from expect_write(200, 1, 20)
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yield from expect_buffer_space_request(0, 1)
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unexpected = yield from get_request()
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self.fail("unexpected packet: {}".format(unexpected))
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def receive(packet_type, field_dict, trailer):
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nonlocal current_request
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self.assertEqual(current_request, None)
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current_request = (packet_type, field_dict, trailer)
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run_simulation(tb.dut,
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{"sys": test(), "rtio": tb.dut.pr.receive(receive), "rtio_rx": send_replies()}, self.clocks)
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