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sayma_amc: fix RTIO TSC instantiation

pull/1231/head
Sebastien Bourdeauducq 2019-01-06 14:54:32 +08:00
parent 6e43c41103
commit 66b3132c28
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/targets/sayma_amc.py
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@ -287,7 +287,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
@ -452,7 +452,7 @@ class Master(MiniSoC, AMPSoC):
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
@ -623,7 +623,7 @@ class Satellite(BaseSoC, RTMCommon):
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())