mirror of https://github.com/m-labs/artiq.git
Merge remote-tracking branch 'origin/master' into new
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commit
c990b5e4f1
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@ -414,48 +414,55 @@ class AD9910:
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self.cpld.io_update.pulse(1*us)
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@kernel
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def tune_sync_delay(self, sync_delay_seed):
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def tune_sync_delay(self, search_seed=15):
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"""Find a stable SYNC_IN delay.
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This method first locates the smallest SYNC_IN validity window at
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minimum window size and then increases the window a bit to provide some
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slack and stability.
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This method first locates a valid SYNC_IN delay at zero validation
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window size (setup/hold margin) by scanning around `search_seed`. It
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then looks for similar valid delays at successively larger validation
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window sizes until none can be found. It then deacreses the validation
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window a bit to provide some slack and stability and returns the
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optimal values.
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It starts scanning delays around `sync_delay_seed` (see the
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device database arguments and :class:`AD9910`) at maximum validation
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window size and decreases the window size until a valid delay is found.
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:param sync_delay_seed: Start value for valid SYNC_IN delay search.
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:param search_seed: Start value for valid SYNC_IN delay search.
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Defaults to 15 (half range).
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:return: Tuple of optimal delay and window size.
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"""
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dt = 14 # 1/(f_SYSCLK*75ps) taps per SYSCLK period
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max_delay = dt # 14*75ps > 1ns
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max_window = dt//4 + 1 # 2*75ps*4 = 600ps high > 1ns/2
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min_window = max(0, max_window - 2) # 2*75ps hold, 2*75ps setup
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for window in range(max_window - min_window + 1):
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window = max_window - window
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for in_delay in range(max_delay):
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# alternate search direction around seed_delay
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search_span = 31
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# FIXME https://github.com/sinara-hw/Urukul/issues/16
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# should both be 2-4 once kasli sync_in jitter is identified
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min_window = 0
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margin = 1 # 1*75ps setup and hold
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for window in range(16):
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next_seed = -1
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for in_delay in range(search_span - 2*window):
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# alternate search direction around search_seed
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if in_delay & 1:
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in_delay = -in_delay
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in_delay = sync_delay_seed + (in_delay >> 1)
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if in_delay < 0:
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in_delay = 0
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elif in_delay > 31:
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in_delay = 31
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in_delay = search_seed + (in_delay >> 1)
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if in_delay < 0 or in_delay > 31:
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continue
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self.set_sync(in_delay, window)
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self.clear_smp_err()
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# integrate SMP_ERR statistics for a few hundred cycles
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delay(10*us)
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delay(100*us)
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err = urukul_sta_smp_err(self.cpld.sta_read())
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err = (err >> (self.chip_select - 4)) & 1
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delay(40*us) # slack
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if not err:
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window -= min_window # add margin
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self.set_sync(in_delay, window)
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self.clear_smp_err()
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delay(40*us) # slack
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return in_delay, window
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if not (err >> (self.chip_select - 4)) & 1:
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next_seed = in_delay
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break
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if next_seed >= 0: # valid delay found, scan next window
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search_seed = next_seed
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continue
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elif window > min_window:
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# no valid delay found here, roll back and add margin
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window = max(min_window, window - 1 - margin)
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self.set_sync(search_seed, window)
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self.clear_smp_err()
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delay(100*us) # slack
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return search_seed, window
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else:
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break
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raise ValueError("no valid window/delay")
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@kernel
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@ -87,36 +87,42 @@ device_db.update({
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"class": "SPIMaster",
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"arguments": {"channel": 27}
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},
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"ttl_urukul0_io_update": {
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"ttl_urukul0_sync": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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"class": "TTLClockGen",
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"arguments": {"channel": 28, "acc_width": 4}
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},
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"ttl_urukul0_sw0": {
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"ttl_urukul0_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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"ttl_urukul0_sw1": {
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"ttl_urukul0_sw0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 30}
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},
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"ttl_urukul0_sw2": {
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"ttl_urukul0_sw1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 31}
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},
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"ttl_urukul0_sw3": {
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"ttl_urukul0_sw2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 32}
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},
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"ttl_urukul0_sw3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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},
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"urukul0_cpld": {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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@ -150,19 +156,19 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 33}
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"arguments": {"channel": 34}
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},
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"ttl_urukul1_sync": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLClockGen",
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"arguments": {"channel": 34, "acc_width": 4}
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"arguments": {"channel": 35, "acc_width": 4}
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},
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"ttl_urukul1_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 35}
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"arguments": {"channel": 36}
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},
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"urukul1_cpld": {
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"type": "local",
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@ -197,13 +203,13 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 36}
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"arguments": {"channel": 37}
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 37}
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"arguments": {"channel": 38}
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}
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})
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@ -213,19 +219,19 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 38}
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"arguments": {"channel": 39}
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},
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"ttl_zotino0_ldac": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 39}
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"arguments": {"channel": 40}
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},
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"ttl_zotino0_clr": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 40}
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"arguments": {"channel": 41}
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},
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"zotino0": {
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"type": "local",
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@ -352,7 +352,7 @@ extern fn dma_record_output_wide(timestamp: i64, target: i32, words: CSlice<i32>
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assert!(words.len() <= 16); // enforce the hardware limit
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unsafe {
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let mut data = dma_record_output_prepare(timestamp, target, 1);
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let mut data = dma_record_output_prepare(timestamp, target, words.len());
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for word in words.as_ref().iter() {
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data[..4].copy_from_slice(&[
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(word >> 0) as u8,
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@ -34,38 +34,39 @@ class _RTIOCRG(Module, AutoCSR):
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clk_synth = platform.request("si5324_clkout_fabric")
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clk_synth_se = Signal()
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clk_synth_buffered = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_buffered),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_buffered,
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=rtio_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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@ -598,7 +599,8 @@ class PTB2(_StandaloneBase):
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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@ -81,8 +81,10 @@ class AD9910Exp(EnvExperiment):
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self.sync_scan(err, win=i)
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print(err)
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self.core.break_realtime()
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dly, win = self.dev.tune_sync_delay(self.dev.sync_delay_seed)
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self.sync_scan(err, win=win + 1) # tighten window by 2*75ps
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dly, win = self.dev.tune_sync_delay()
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self.sync_scan(err, win=win)
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# FIXME: win + 1 # tighten window by 2*75ps
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# after https://github.com/sinara-hw/Urukul/issues/16
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self.set_dataset("dly", dly)
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self.set_dataset("win", win)
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self.set_dataset("err", err)
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@ -92,7 +94,7 @@ class AD9910Exp(EnvExperiment):
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for in_delay in range(len(err)):
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self.dev.set_sync(in_delay=in_delay, window=win)
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self.dev.clear_smp_err()
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delay(10*us) # integrate SMP_ERR statistics
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# delay(10*us) # integrate SMP_ERR statistics
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e = urukul_sta_smp_err(self.dev.cpld.sta_read())
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err[in_delay] = (e >> (self.dev.chip_select - 4)) & 1
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delay(50*us) # slack
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