grabber: add false path constraints

artiq/gateware/eem.py

@@ -414,6 +414,14 @@ class Grabber(_EEM):
         phy = grabber.Grabber(pads)
         name = "grabber{}".format(len(target.grabber_csr_group))
         setattr(target.submodules, name, phy)
+
+        target.platform.add_false_path_constraints(
+            target.crg.cd_sys.clk, phy.deserializer.cd_cl.clk)
+        # Avoid bogus s/h violations at the clock input being sampled
+        # by the ISERDES. This uses dynamic calibration.
+        target.platform.add_false_path_constraints(
+            pads.clk_p, phy.deserializer.cd_cl7x.clk)
+
         target.grabber_csr_group.append(name)
         target.csr_devices.append(name)
         target.rtio_channels += [