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sayma: put RTM clock tree into the siphaser loop
* Fixes one bug where siphaser was one Si5324 output and the rest of the system was clocked by the other. With the Si5324 settings we have, skew between the outputs is not controlled. * Puts the coaxial cable between AMC and RTM into the siphaser loop.
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@ -176,7 +176,7 @@ pub mod hmc7043 {
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(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
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(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
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(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
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(false, 0, 0x10), // 11: FPGA_ADC_SYSREF, LVDS
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(true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
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(false, 0, 0x08), // 12: ADC1_CLK
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(false, 0, 0x08), // 13: ADC1_SYSREF
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];
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@ -278,7 +278,7 @@ pub extern fn main() -> i32 {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
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let mut ad9154_initialized = false;
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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@ -289,6 +289,13 @@ pub extern fn main() -> i32 {
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info!("link is up, switching to recovered clock");
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si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::siphaser::calibrate_skew(SIPHASER_PHASE).expect("failed to calibrate skew");
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#[cfg(has_ad9154)]
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{
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if !ad9154_initialized {
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board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
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ad9154_initialized = true;
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}
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}
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drtioaux::reset(0);
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drtio_reset(false);
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drtio_reset_phy(false);
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@ -573,7 +573,7 @@ class Satellite(BaseSoC, RTMCommon):
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
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si5324_clkout_fabric=platform.request("adc_sysref"))
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
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mmcm_ps=self.siphaser.mmcm_ps_output)
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platform.add_false_path_constraints(
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