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jesd204_tools: get the Vivado timing analyzer to behave
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@ -37,6 +37,7 @@ class UltrascaleCRG(Module, AutoCSR):
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]
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if use_rtio_clock:
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self.cd_jesd.clk.attr.add("keep")
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self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
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else:
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self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)
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