mirror of https://github.com/m-labs/artiq.git
drtio: improve error reporting
This commit is contained in:
parent
95432a4ac1
commit
edf403b837
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@ -260,7 +260,11 @@ fn drtiosat_process_errors() {
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error!("received truncated packet");
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}
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if errors & 4 != 0 {
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error!("timeout attempting to get buffer space from CRI")
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let destination;
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unsafe {
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destination = csr::drtiosat::buffer_space_timeout_dest_read();
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}
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error!("timeout attempting to get buffer space from CRI, destination=0x{:02x}", destination)
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}
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if errors & 8 != 0 {
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let channel;
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@ -2,10 +2,10 @@ use board_misoc::{csr, clock};
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use board_artiq::{drtioaux, drtio_routing};
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#[cfg(has_drtio_routing)]
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fn rep_link_rx_up(linkno: u8) -> bool {
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let linkno = linkno as usize;
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fn rep_link_rx_up(repno: u8) -> bool {
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let repno = repno as usize;
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unsafe {
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(csr::DRTIOREP[linkno].rx_up_read)() == 1
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(csr::DRTIOREP[repno].rx_up_read)() == 1
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}
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}
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@ -40,6 +40,8 @@ impl Repeater {
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}
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pub fn service(&mut self, routing_table: &drtio_routing::RoutingTable, rank: u8) {
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self.process_errors();
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match self.state {
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RepeaterState::Down => {
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if rep_link_rx_up(self.repno) {
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@ -109,6 +111,37 @@ impl Repeater {
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}
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}
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fn process_errors(&self) {
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let repno = self.repno as usize;
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let errors;
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unsafe {
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errors = (csr::DRTIOREP[repno].protocol_error_read)();
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}
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if errors & 1 != 0 {
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error!("[REP#{}] received packet of an unknown type", repno);
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}
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if errors & 2 != 0 {
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error!("[REP#{}] received truncated packet", repno);
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}
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if errors & 4 != 0 {
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let chan_sel;
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unsafe {
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chan_sel = (csr::DRTIOREP[repno].command_missed_chan_sel_read)();
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}
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error!("[REP#{}] CRI command missed, chan_sel=0x{:06x}", repno, chan_sel)
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}
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if errors & 8 != 0 {
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let destination;
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unsafe {
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destination = (csr::DRTIOREP[repno].buffer_space_timeout_dest_read)();
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}
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error!("[REP#{}] timeout attempting to get remote buffer space, destination=0x{:02x}", repno, destination);
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}
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unsafe {
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(csr::DRTIOREP[repno].protocol_error_write)(errors);
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}
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}
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fn recv_aux_timeout(&self, timeout: u32) -> Result<drtioaux::Packet, &'static str> {
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let max_time = clock::get_ms() + timeout as u64;
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loop {
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@ -143,7 +143,7 @@ class DRTIOSatellite(Module):
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]
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self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
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self.rt_packet, tsc, self.cri, self.async_errors)
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self.rt_packet, tsc, self.async_errors)
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def get_csrs(self):
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return ([self.reset, self.reset_phy, self.tsc_loaded] +
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@ -10,6 +10,8 @@ class RTController(Module, AutoCSR):
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def __init__(self, rt_packet):
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self.set_time = CSR()
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self.protocol_error = CSR(4)
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self.command_missed_chan_sel = CSRStatus(24)
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self.buffer_space_timeout_dest = CSRStatus(8)
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set_time_stb = Signal()
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set_time_ack = Signal()
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@ -23,14 +25,21 @@ class RTController(Module, AutoCSR):
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self.comb += self.set_time.w.eq(set_time_stb)
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errors = [
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(rt_packet.err_unknown_packet_type, "rtio_rx"),
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(rt_packet.err_packet_truncated, "rtio_rx"),
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(rt_packet.err_command_missed, "rtio"),
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(rt_packet.err_buffer_space_timeout, "rtio")
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(rt_packet.err_unknown_packet_type, "rtio_rx", None, None),
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(rt_packet.err_packet_truncated, "rtio_rx", None, None),
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(rt_packet.err_command_missed, "rtio",
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rt_packet.cri.chan_sel, self.command_missed_chan_sel.status),
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(rt_packet.err_buffer_space_timeout, "rtio",
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rt_packet.buffer_space_destination, self.buffer_space_timeout_dest.status)
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]
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for n, (err_i, err_cd) in enumerate(errors):
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xfer = BlindTransfer(err_cd, "sys")
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for n, (err_i, err_cd, din, dout) in enumerate(errors):
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if din is not None:
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data_width = len(din)
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else:
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data_width = 0
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xfer = BlindTransfer(err_cd, "sys", data_width=data_width)
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self.submodules += xfer
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self.comb += xfer.i.eq(err_i)
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@ -41,3 +50,7 @@ class RTController(Module, AutoCSR):
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If(xfer.o, err_pending.eq(1))
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]
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self.comb += self.protocol_error.w[n].eq(err_pending)
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if din is not None:
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self.comb += xfer.data_i.eq(din)
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self.sync += If(xfer.o & ~err_pending, dout.eq(xfer.data_o))
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@ -7,11 +7,12 @@ from artiq.gateware.rtio.cdc import BlindTransfer
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class RTErrorsSatellite(Module, AutoCSR):
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def __init__(self, rt_packet, tsc, cri, async_errors):
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def __init__(self, rt_packet, tsc, async_errors):
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self.protocol_error = CSR(5)
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self.underflow_channel = CSRStatus(16)
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self.underflow_timestamp_event = CSRStatus(64)
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self.underflow_timestamp_counter = CSRStatus(64)
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self.buffer_space_timeout_dest = CSRStatus(8)
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self.rtio_error = CSR(3)
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self.sequence_error_channel = CSRStatus(16)
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@ -47,6 +48,7 @@ class RTErrorsSatellite(Module, AutoCSR):
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self.comb += xfer.data_i.eq(din)
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self.sync += If(xfer.o & ~pending, dout.eq(xfer.data_o))
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cri = rt_packet.cri
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# The master is normally responsible for avoiding output overflows
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# and output underflows. The error reports here are only for diagnosing
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@ -68,7 +70,8 @@ class RTErrorsSatellite(Module, AutoCSR):
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error_csr(self.protocol_error,
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(rt_packet.unknown_packet_type, False, None, None),
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(rt_packet.packet_truncated, False, None, None),
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(rt_packet.buffer_space_timeout, False, None, None),
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(rt_packet.buffer_space_timeout, False,
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cri.chan_sel[16:], self.buffer_space_timeout_dest.status),
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(underflow, True, underflow_error_cri, underflow_error_csr),
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(overflow, True, None, None)
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)
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@ -20,6 +20,7 @@ class RTPacketRepeater(Module):
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# in rtio domain
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self.err_command_missed = Signal()
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self.err_buffer_space_timeout = Signal()
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self.buffer_space_destination = Signal(8)
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# set_time interface, in rtio domain
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self.set_time_stb = Signal()
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@ -85,9 +86,8 @@ class RTPacketRepeater(Module):
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)
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# Buffer space
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buffer_space_destination = Signal(8)
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self.sync.rtio += If(self.cri.cmd == cri.commands["get_buffer_space"],
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buffer_space_destination.eq(self.cri.chan_sel[16:]))
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self.buffer_space_destination.eq(self.cri.chan_sel[16:]))
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rx_buffer_space_not = Signal()
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rx_buffer_space = Signal(16)
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@ -153,7 +153,7 @@ class RTPacketRepeater(Module):
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)
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)
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tx_fsm.act("BUFFER_SPACE",
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tx_dp.send("buffer_space_request", destination=buffer_space_destination),
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tx_dp.send("buffer_space_request", destination=self.buffer_space_destination),
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If(tx_dp.packet_last,
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buffer_space_not_ack.eq(1),
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NextState("WAIT_BUFFER_SPACE")
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@ -144,6 +144,7 @@ class RTPacketSatellite(Module):
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NextState("INPUT")
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)
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# CRI mux defaults to write information
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rx_fsm.act("WRITE",
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If(write_data_buffer_cnt == rx_dp.packet_as["write"].extra_data_cnt,
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NextState("WRITE_CMD")
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@ -170,6 +171,7 @@ class RTPacketSatellite(Module):
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NextState("BUFFER_SPACE")
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)
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rx_fsm.act("BUFFER_SPACE",
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cri_buffer_space.eq(1),
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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self.buffer_space_timeout.eq(1),
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