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kasli: DRTIO Base: flexible rtio_clk_freq
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parent
eb9e9634df
commit
9584c30a1f
@ -626,7 +626,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -638,7 +638,6 @@ class _MasterBase(MiniSoC, AMPSoC):
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -760,7 +759,7 @@ class _SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -769,7 +768,6 @@ class _SatelliteBase(BaseSoC):
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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@ -803,7 +801,8 @@ class _SatelliteBase(BaseSoC):
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric"),
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ref_clk=self.crg.clk125_div2, ref_div2=True)
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ref_clk=self.crg.clk125_div2, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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