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artiq
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grabber: add clock constraint

pull/1104/merge
Sebastien Bourdeauducq 2018-07-10 12:37:32 +08:00
parent d51294649e
commit c4e3c66265
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/eem.py
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@ -409,8 +409,9 @@ class Grabber(_EEM):
def add_std(cls, target, eem, eem_aux=None, ttl_out_cls=None):
cls.add_extension(target, eem, eem_aux)
phy = grabber.Grabber(target.platform.request(
"grabber{}_video".format(eem)))
pads = target.platform.request("grabber{}_video".format(eem))
target.platform.add_period_constraint(pads.clk_p, 14.71)
phy = grabber.Grabber(pads)
name = "grabber{}".format(len(target.grabber_csr_group))
setattr(target.submodules, name, phy)
target.grabber_csr_group.append(name)