mirror of https://github.com/m-labs/artiq.git
drtio: minor cleanup
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parent
ce6e390d5f
commit
4f963e1e11
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@ -156,7 +156,7 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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def __init__(self, chanif, channel_count=1024, fine_ts_width=3):
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def __init__(self, chanif, fine_ts_width=3):
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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@ -164,9 +164,8 @@ class DRTIOMaster(Module):
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller_master.RTController(
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self.rt_packet, channel_count, fine_ts_width)
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self.rt_packet, fine_ts_width)
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self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
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self.cri = self.rt_controller.cri
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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@ -177,3 +176,7 @@ class DRTIOMaster(Module):
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs() +
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self.aux_controller.get_csrs())
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@property
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def cri(self):
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return self.rt_controller.cri
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@ -45,7 +45,7 @@ class RTIOCounter(Module):
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class RTController(Module):
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def __init__(self, rt_packet, channel_count, fine_ts_width):
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def __init__(self, rt_packet, fine_ts_width):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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