mirror of https://github.com/m-labs/artiq.git
kasli: remove unpopulated Tester EEMs
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester) * shortens compilation times
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@ -189,156 +189,18 @@ device_db["zotino0"] = {
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}
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# Grabber (EEM6) starting at RTIO channel 25
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device_db["grabber0"] = {
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"type": "local",
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"module": "artiq.coredevice.grabber",
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"class": "Grabber",
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"arguments": {"channel_base": 25}
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}
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# Urukul (EEM7) starting at RTIO channel 27
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device_db.update(
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spi_urukul1={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 27}
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},
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ttl_urukul1_sync={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLClockGen",
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"arguments": {"channel": 28, "acc_width": 4}
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},
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ttl_urukul1_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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urukul1_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul1",
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"io_update_device": "ttl_urukul1_io_update",
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"sync_device": "ttl_urukul1_sync",
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"refclk": 100e6,
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"clk_sel": 1
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}
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}
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)
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for i in range(4):
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device_db["urukul1_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 4 + i,
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"cpld_device": "urukul1_cpld"
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}
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}
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# DIO (EEM8) starting at RTIO channel 30
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for i in range(8):
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device_db["ttl" + str(8 + i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 30 + i},
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}
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# DIO (EEM9) starting at RTIO channel 38
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for i in range(8):
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device_db["ttl" + str(16 + i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 38 + i},
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}
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# Sampler (EEM10) starting at RTIO channel 46
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device_db["spi_sampler1_adc"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 46}
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}
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device_db["spi_sampler1_pgia"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 47}
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}
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device_db["spi_sampler1_cnv"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 48},
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}
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device_db["sampler1"] = {
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"type": "local",
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"module": "artiq.coredevice.sampler",
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"class": "Sampler",
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"arguments": {
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"spi_adc_device": "spi_sampler1_adc",
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"spi_pgia_device": "spi_sampler1_pgia",
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"cnv_device": "spi_sampler1_cnv"
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}
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}
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# Zotino (EEM11) starting at RTIO channel 49
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device_db["spi_zotino1"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 49}
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}
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device_db["ttl_zotino1_ldac"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 50}
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}
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device_db["ttl_zotino1_clr"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 51}
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}
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device_db["zotino1"] = {
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"type": "local",
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"module": "artiq.coredevice.zotino",
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"class": "Zotino",
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"arguments": {
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"spi_device": "spi_zotino1",
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"ldac_device": "ttl_zotino1_ldac",
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"clr_device": "ttl_zotino1_clr"
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}
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}
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device_db.update(
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led0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 52}
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"arguments": {"channel": 25}
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},
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led1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 53}
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"arguments": {"channel": 26}
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},
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)
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@ -774,7 +774,6 @@ class Tester(_StandaloneBase):
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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self.grabber_csr_group = []
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
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edge_counter_cls=edge_counter.SimpleEdgeCounter)
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@ -782,15 +781,6 @@ class Tester(_StandaloneBase):
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ttl_simple.ClockGen)
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eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
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eem.Grabber.add_std(self, 6)
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eem.Urukul.add_std(self, 7, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.DIO.add_std(self, 8,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 9,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 10, None, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 11, ttl_serdes_7series.Output_8X)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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@ -803,11 +793,6 @@ class Tester(_StandaloneBase):
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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