mirror of https://github.com/m-labs/artiq.git
grabber: minor ROI engine cleanup, export count_len, cap count width to 31
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766d87f626
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@ -50,7 +50,7 @@ assert len(set(bitseq)) == 24
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class Parser(Module, AutoCSR):
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"""Parses 28 bit encoded words and track pixel coordinates."""
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def __init__(self, width=12):
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def __init__(self, width):
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self.cl = cl = Signal(28)
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self.last_x = CSRStatus(width)
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@ -110,8 +110,14 @@ class Parser(Module, AutoCSR):
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class ROI(Module):
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"""ROI Engine. For each frame, accumulates pixels values within a
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rectangular region of interest, and reports the total."""
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def __init__(self, pix, shift=0):
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cnt_len = len(pix.x) + len(pix.y) + 16 - shift
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@staticmethod
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def count_len(width, shift):
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# limit width to 31 to avoid problems with CPUs and RTIO inputs
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return min(31, 2*width + 16 - shift)
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def __init__(self, pix, shift):
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count_len = ROI.count_len(len(pix.x), shift)
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self.cfg = cfg = Record([
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("x0", len(pix.x)),
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@ -121,8 +127,8 @@ class ROI(Module):
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])
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self.out = out = Record([
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("update", 1),
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# register output - can be used as CDC input
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("cnt", cnt_len),
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# registered output - can be used as CDC input
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("count", count_len),
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])
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# # #
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@ -156,16 +162,16 @@ class ROI(Module):
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]
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# stage 2 - accumulate
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cnt = Signal(cnt_len)
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count = Signal(count_len)
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self.sync.cl += [
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If(stb & x_good & y_good,
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cnt.eq(cnt + gray),
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count.eq(count + gray),
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),
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out.update.eq(0),
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If(eop,
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cnt.eq(0),
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out.update.eq(1),
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out.cnt.eq(cnt)
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out.count.eq(count)
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)
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]
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